欧美成人免费电影,国产欧美一区二区三区精品酒店,精品国产a毛片,色网在线免费观看

參數資料
型號: EP1K50QC208-1
廠商: Altera
文件頁數: 19/86頁
文件大小: 0K
描述: IC ACEX 1K FPGA 50K 208-PQFP
產品培訓模塊: Three Reasons to Use FPGA's in Industrial Designs
標準包裝: 144
系列: ACEX-1K®
LAB/CLB數: 360
邏輯元件/單元數: 2880
RAM 位總計: 40960
輸入/輸出數: 147
門數: 199000
電源電壓: 2.375 V ~ 2.625 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 70°C
封裝/外殼: 208-BFQFP
供應商設備封裝: 208-PQFP(28x28)
其它名稱: 544-1007
26
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
FastTrack Interconnect Routing Structure
In the ACEX 1K architecture, connections between LEs, EABs, and device
I/O pins are provided by the FastTrack Interconnect routing structure,
which is a series of continuous horizontal and vertical routing channels
that traverse the device. This global routing structure provides
predictable performance, even in complex designs. In contrast, the
segmented routing in FPGAs requires switch matrices to connect a
variable number of routing paths, increasing the delays between logic
resources and reducing performance.
The FastTrack Interconnect routing structure consists of row and column
interconnect channels that span the entire device. Each row of LABs is
served by a dedicated row interconnect. The row interconnect can drive
I/O pins and feed other LABs in the row. The column interconnect routes
signals between rows and can drive I/O pins.
Row channels drive into the LAB or EAB local interconnect. The row
signal is buffered at every LAB or EAB to reduce the effect of fan-out on
delay. A row channel can be driven by an LE or by one of three column
channels. These four signals feed dual 4-to-1 multiplexers that connect to
two specific row channels. These multiplexers, which are connected to
each LE, allow column channels to drive row channels even when all eight
LEs in a LAB drive the row interconnect.
Each column of LABs or EABs is served by a dedicated column
interconnect. The column interconnect that serves the EABs has twice as
many channels as other column interconnects. The column interconnect
can then drive I/O pins or another row’s interconnect to route the signals
to other LABs or EABs in the device. A signal from the column
interconnect, which can be either the output of a LE or an input from an
I/O pin, must be routed to the row interconnect before it can enter a LAB
or EAB. Each row channel that is driven by an IOE or EAB can drive one
specific column channel.
Access to row and column channels can be switched between LEs in
adjacent pairs of LABs. For example, a LE in one LAB can drive the row
and column channels normally driven by a particular LE in the adjacent
LAB in the same row, and vice versa. This flexibility enables routing
resources to be used more efficiently. Figure 13 shows the ACEX 1K LAB.
相關PDF資料
PDF描述
ADM1032ARMZ-2 IC TEMP MONITOR 85DEG 8MSOP
AMM18DRMN-S288 CONN EDGECARD 36POS .156 EXTEND
RSO-2405D/H3 CONV DC/DC 1W 18-36VIN +/-05VOUT
EP1K100FC484-2 IC ACEX 1K FPGA 100K 484-FBGA
D15P13F6GL00LF CONN DSUB PLUG 15POS T/H RA GOLD
相關代理商/技術參數
參數描述
EP1K50QC208-1DX 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
EP1K50QC208-1F 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
EP1K50QC208-1N 功能描述:FPGA - 現場可編程門陣列 FPGA - ACEX 1K 360 LABs 147 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1K50QC208-1P 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
EP1K50QC208-1X 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
主站蜘蛛池模板: 民勤县| 汽车| 民乐县| 新泰市| 门头沟区| 昭觉县| 凤庆县| 大方县| 湟源县| 宝坻区| 邹平县| 龙南县| 漳浦县| 莱州市| 汉川市| 上饶市| 舒城县| 博野县| 科技| 白河县| 博兴县| 兴隆县| 沅陵县| 新竹市| 乐都县| 望都县| 利辛县| 台山市| 宁南县| 沾益县| 台中市| 巴马| 怀柔区| 清水河县| 柳河县| 闽侯县| 明水县| 乐亭县| 乌什县| 兴仁县| 遂昌县|