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參數(shù)資料
| 型號(hào)： | F369GA |
| 廠商： | Fujitsu Limited |
| 英文描述： | 32-BIT RISC MICROCONTROLLER |
| 中文描述： | 32位RISC微控制器 |
| 文件頁(yè)數(shù)： | 174/206頁(yè) |
| 文件大小： | 811K |
| 代理商： | F369GA |
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MB91360G Series
174
(8) Notes to Use of Flash Memory
Notes on the Flash Memory in MB91360G series devices are given below.
a
:
Input of hardware reset
(INITX)
To input a hardware reset when the automatic algorithm is not started, where reading is in progress, a minimum
of 500 ns should be taken at a low-level width. In this case, a maximum of 500 ns is required until data can be
read from the flash memory after a hardware reset has been activated.
Similarly, to input a hardware reset when the automatic algorithm is activated, where writing/erasing is in
progress, a minimum of 50 ns should be taken in a low-level width. In this case, 20
μ
s are required until data
can be read after the executing operation has been terminated to initialize the flash memory.
A hardware reset during writing undefined data being written. A hardware reset during erasing may make the
sector being erased unusable.
b
:
Canceling software reset
,
watchdog timer reset
,
and hardware standby
When writing/erasing the flash memory with the CPU access and if reset conditions occur while the automatic
algorithm is active, the CPU may run away. This occurs because these reset conditions cause the automatic
algorithm to continue without initializing the flash memory unit, possibly preventing the flash memory unit from
entering the read state when the CPU starts the sequence after the reset has been deasserted. These reset
conditions should be inhibited during writing/erasing the Flash Memory.
c
:
Program access to Flash Memory
When the automatic algorithm is operating, read access to the flash memory is disabled. With the memory
access mode of the CPU set to the internal ROM mode, writing/erasing should be started after switching the
program area to another area such as RAM.
In this case, when sectors containing interrupt vectors are erased, interrupt processing cannot be executed.
For the same reason, all interrupt sources should be disabled while the automatic algorithm is operating.
d
:
Hold function
When the CPU accepts a hold request, the Write signal WE of the flash memory unit may be skewed and many
cause erroneous writing/erasing. When the acceptance of a hold request is enabled, ensure that the WE bit of
the control status register (FMCS) is 0.
e
:
Applying V
ID
Applying V
ID
required for the sector protect operation should always be started and terminated when the supply
voltage is on.
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