- 您現在的位置：買賣IC網 > PDF目錄375705 > F49L400BA (Elite Semiconductor Memory Technology Inc.) 4 Mbit (512K x 8/256K x 16) 3V Only CMOS Flash Memory PDF資料下載
參數資料
| 型號： | F49L400BA |
| 廠商： | Elite Semiconductor Memory Technology Inc. |
| 英文描述： | 4 Mbit (512K x 8/256K x 16) 3V Only CMOS Flash Memory |
| 中文描述： | 4兆位（為512k × 8/256K × 16）3V時僅閃存的CMOS |
| 文件頁數： | 17/47頁 |
| 文件大小： | 397K |
| 代理商： | F49L400BA |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁當前第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁
EFS T
7.4 More Device Operations
Hardware Data Protection
F49L400UA/F49L400BA
Elite Flash Storage Technology Inc.
Publication Date : Sep. 2006
Revision: 1.1 17/47
The command sequence requirement of unlock cycles for
programming or erasing provides data protection against
inadvertent writes. In addition, the following hardware
data protection measures prevent accidental erasure or
programming, which might otherwise be caused by
spurious system level signals during V
CC
power-up and
power-down transitions, or from system noise.
Low V
CC
Write Inhibit
When V
CC
is less than VLKO, the device does not accept
any write cycles. This protects data during V
CC
power-up
and power-down. The command register and all internal
program/erase circuits are disabled, and the device
resets. Subsequent writes are ignored until V
CC
is
greater than V
LKO
. The system must provide the proper
signals to the control pins to prevent unintentional writes
when V
CC
is greater than V
LKO
.
Write Pulse "Glitch" Protection
Noise pulses of less than 5 ns (typical) on
CE
or
WE
do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of
OE
=
V
IL
,
CE
= V
IH
or
WE
= V
IH
. To initiate a write cycle,
CE
and
WE
must be a logical zero while
OE
is a
logical one.
Power Supply Decoupling
In order to reduce power switching effect, each device
should have a 0.1uF ceramic capacitor connected
between
its V
CC
and GND.
Power-Up Sequence
The device powers up in the Read Mode. In addition, the
memory contents may only be altered after successful
completion of the predefined command sequences.
Power-Up Write Inhibit
If
WE
=
CE
= V
IL
and
OE
= V
IH
during power up, the
device does not accept commands on the rising edge of
WE
. The internal state machine is automatically reset to
reading array data on power-up.
相關PDF資料 |
PDF描述 |
|---|---|
| F49L400BA-70T | 4 Mbit (512K x 8/256K x 16) 3V Only CMOS Flash Memory |
| F49L400BA-90T | 4 Mbit (512K x 8/256K x 16) 3V Only CMOS Flash Memory |
| F49L400UA | 4 Mbit (512K x 8/256K x 16) 3V Only CMOS Flash Memory |
| F49L400UA-70T | 4 Mbit (512K x 8/256K x 16) 3V Only CMOS Flash Memory |
| F49L400UA-90T | 4 Mbit (512K x 8/256K x 16) 3V Only CMOS Flash Memory |
相關代理商/技術參數 |
參數描述 |
|---|---|
| F49L400BA-70T | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:4 Mbit (512K x 8/256K x 16) 3V Only CMOS Flash Memory |
| F49L400BA-90T | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:4 Mbit (512K x 8/256K x 16) 3V Only CMOS Flash Memory |
| F49L400UA | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:4 Mbit (512K x 8/256K x 16) 3V Only CMOS Flash Memory |
| F49L400UA-70T | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:4 Mbit (512K x 8/256K x 16) 3V Only CMOS Flash Memory |
發布緊急采購，3分鐘左右您將得到回復。