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參數資料
| 型號： | FAN5009MX |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | MOSFETs |
| 英文描述： | Dual Bootstrapped 12V MOSFET Driver |
| 中文描述： | HALF BRDG BASED MOSFET DRIVER, PDSO8 |
| 封裝： | 0.150 INCH, SOIC-8 |
| 文件頁數： | 2/13頁 |
| 文件大小： | 167K |
| 代理商： | FAN5009MX |
2
REV. 1.0.5 7/22/04
FAN5009
PRODUCT SPECIFICATION
Pin Configuration
Pin Definitions
Functional Block Diagram
Pin #
Pin Name
Pin Function Description
1
BOOT
Bootstrap Supply Input.
bootstrap capacitor. See Applications Section.
PWM Signal Input.
This pin accepts a logic-level PWM signal from the controller.
Output Disable.
When low, this pin disables FET switching (HDRV and LDRV are held low).
Power Input
. +12V chip bias power. Bypass with a 1μF ceramic capacitor.
Low Side Gate Drive Output.
Connect to the gate of low-side power MOSFET(s).
Power ground.
Connect directly to source of low-side MOSFET(s).
Switch Node Input
. Connect as shown in Figure 1. SW provides return for high-side
bootstrapped driver and acts as a sense point for the adaptive shoot-thru protection.
High Side Gate Drive Output
–
Connect to the gate of high-side power MOSFET(s).
Provides voltage supply to high-side MOSFET driver. Connect to
2
3
4
5
6
7
PWM
OD
VCC
LDRV
PGND
SW
8
HDRV
BOOT
PWM
OD
VCC
FAN5009
1
2
3
4
8
7
6
5
HDRV
SW
PGND
LDRV
FAN5009M 8-pin SO-8 package
BOOT
PWM
OD
VCC
FAN5009
1
2
3
4
8
7
6
5
HDRV
Paddle
(Ground)
SW
PGND
LDRV
FAN5009MP 8-pin MLP package
(Paddle should be connected to ground or left floating)
PWM
2
OD
3
2.2
1.2
1
BOOT
VCC
4
SW
7
+
VCC
6
5
LDRV
PGND
8
HDRV
1.2
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