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參數資料
| 型號： | FAN5009MX |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | MOSFETs |
| 英文描述： | Dual Bootstrapped 12V MOSFET Driver |
| 中文描述： | HALF BRDG BASED MOSFET DRIVER, PDSO8 |
| 封裝： | 0.150 INCH, SOIC-8 |
| 文件頁數： | 9/13頁 |
| 文件大小： | 167K |
| 代理商： | FAN5009MX |
PRODUCT SPECIFICATION
FAN5009
REV. 1.0.5 7/22/04
9
Thermal Considerations
Total device dissipation:
where P
Q
represents quiescent power dissipation:
where F
SW
is switching frequency (in kHz).
P
R
is power dissipated in the bootstrap rectifier:
Where Q
G1
is total gate charge of the upper FET (Q1) for
it’s applied V
GS
.
V
F
for the applied I
F(AVG)
can be graphically determined
using the datasheet curves, where:
P
HDRV
represents internal power dissipation of the upper
FET driver.
Where P
H(R)
and P
H(F)
are internal dissipations for the
rising and falling edges, respectively:
where:
As described in eq. 8 and 9 above, the total power consumed
in driving the gate is divided in proportion to the resistances
in series with the MOSFET's internal gate node as shown
below:
Figure 5. Driver dissipation model
R
G
is the polysilicon gate resistance, internal to the FET.
R
E
is the external gate drive resistor implemented in many
designs. Note that the introduction of R
E
can reduce driver
power dissipation, but excess R
E
may cause errors in the
“adaptive gate drive” circuitry. For more information please
refer to Fairchild app note AN-6003, “Shoot-through” in
Synchronous Buck Converters.
P
LDRV
is dissipation of the lower FET driver.
Where P
H(R)
and P
H(F)
are internal dissipations for the
rising and falling edges, respectively:
where:
Layout Considerations
Use the following general guidelines when designing printed
circuit boards (see Figures 6 and 7):
1.
Trace out the high-current paths and use short, wide
(>25 mil) traces to make these connections.
2.
Connect the PGND pin of the FAN5009 as close as
possible to the source of the lower MOSFET.
3.
The V
CC
bypass capacitor should be located as close as
possible to V
CC
and PGND pins.
Use vias to other layers when possible to maximize
thermal conduction away from the IC.
4.
Figure 6. External component placement
recommendation for SO8 package (not to scale)
P
D
P
Q
P
R
P
HDRV
P
LDRV
+
+
+
=
(3)
P
Q
V
CC
4mA + 0.036 F
SW
100
–
)
[
]
×
=
(4)
P
R
V
F
F
SW
×
Q
G1
×
=
(5)
I
F AVG
)
F
SW
Q
G1
×
=
(6)
P
HDRV
P
H R
P
H F
( )
+
=
(7)
P
H R
P
Q1
R
E
R
R
E
+
HUP
R
G
+
---------------+
×
=
(8)
P
H F
( )
P
Q1
R
HDN
R
G
+
----------------------------------------
×
=
(9)
P
Q1
1
2
--
Q
×
G1
V
GS Q1
)
F
SW
×
×
=
(10)
HDRV
Q1
G
R
G
R
E
R
HUP
BOOT
SW
R
HDN
S
P
LDRV
P
L R
P
L F
( )
+
=
(11)
P
L R
P
Q2
R
R
E
+
R
LUP
R
G
+
---------------------------------------
×
=
(12)
P
L F
P
Q2
R
R
E
+
R
HDN
R
G
+
----------------------------------------
×
=
(13)
P
Q2
1
2
--
Q
×
G2
V
GS Q2
)
F
SW
×
×
=
(14)
1
2
3
4
8
7
6
5
C
BOOT
C
VCC
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