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參數(shù)資料
| 型號(hào)： | FAN5018BMTCX |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 6-Bit VID Controller 2-4 Phase VR10.X Controller |
| 中文描述： | SWITCHING CONTROLLER, 4000 kHz SWITCHING FREQ-MAX, PDSO28 |
| 封裝： | LEAD FREE, MO-153AB, TSSOP-28 |
| 文件頁(yè)數(shù)： | 23/30頁(yè) |
| 文件大?。?/td> | 509K |
| 代理商： | FAN5018BMTCX |
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PRODUCT SPECIFICATION
FAN501
8
B
REV. 1.0.0 Jul/15/05
23
Typically, for main MOSFETs, one wants the highest
speed (low C
ISS
) device, but these usually have higher
ON-resistance. Select a device that meets the total power
dissipation (about 1.5 W for a single D-PAK) when combin-
ing the switching and conduction losses.
For our example, we have selected a Fairchild FD6696 as the
main MOSFET (three total; n
MF
= 3), with a C
iss
= 2058 pF
(max) and R
DS(MF)
= 15m (max at T
J
= 125oC) and a
Fairchild FDD6682 as the synchronous MOSFET (six total;
n
SF
= 6), with C
iss
= 2880pF (max) and R
DS(SF)
= 11.9m
Ω
(max at T
J
= 125oC). The synchronous MOSFET C
iss
is less
than 3000 pF, satisfying that requirement. Solving for the
power dissipation per MOSFET at I
O
= 65A and I
R
= 8.86A
yields 1.24W for each synchronous MOSFET and 1.62W for
each main MOSFET. These numbers work well considering
there is usually more PCB area available for each main
MOSFET versus each synchronous MOSFET.
One last item to look at is the power dissipation in the driver
for each phase. This is best described in terms of the Q
G
for
the MOSFETs and is given by the following, where Q
GMF
is
the total gate charge for each main MOSFET and Q
GSF
is the
total gate charge for each synchronous MOSFET:
Also shown is the standby dissipation factor (I
CC
times the
V
CC
) for the driver. For the FAN5009, the maximum dissipa-
tion should be less than 400 mW. For our example, with
I
CC
= 7 mA, Q
GMF
= 24nC (max) and Q
GSF
= 31nC (max),
we find 202 mW in each driver, which is below the 400 mW
dissipation limit. See the FAN5009 data sheet for more
details.
Ramp Resistor Selection
The ramp resistor (R
R
) is used for setting the size of the
internal PWM ramp. This resistor’s value is chosen to pro-
vide the best combination of thermal balance, stability, and
transient response. The following expression is used for
determining the optimum value:
where A
R
is the internal ramp amplifier gain, A
D
is the
current balancing amplifier gain, R
DS
is the total low-side
MOSFET ON-resistance, and C
R
is the internal ramp
capacitor value. A close standard 1% resistor value is 301k
Ω
.
The internal ramp voltage magnitude can be calculated
using:
The size of the internal ramp can be made larger or smaller.
If it is made larger, stability and transient response will
improve, but thermal balance will degrade. Likewise, if the
ramp is made smaller, thermal balance will improve at the
sacrifice of transient response and stability. The factor of
three in the denominator of equation 19 sets a ramp size that
gives an optimal balance for good stability, transient
response, and thermal balance.
COMP Pin Ramp
There is a ramp signal on the COMP pin due to the droop
voltage and output voltage ramps. This ramp amplitude adds
to the internal ramp to produce the following overall ramp
signal at the PWM input.
For this example, the overall ramp signal is found to be
0.974V.
Current Limit Set Point
To select the current limit set point, we need to find the
resistor value for R
LIM
. The current limit threshold for the
FAN5018B is set with a 3V source (V
LIM
) across R
LIM
with
a gain of 10.4mV/mA (A
LIM
). R
LIM
can be found using the
following:
For R
LIM
values greater than 500k
Ω
, the current limit may be
lower than expected, so some adjustment of R
LIM
may be
needed. Here, I
LIM
is the average current limit for the output
of the supply. For our example, choosing 120A for I
LIM
, we
find R
LIM
to be 200k
Ω
, for which we chose 200k
Ω
as the
nearest 1% value.
The per phase current limit described earlier has its limit
determined by the following:
For the FAN5018B, the maximum COMP voltage
(V
COMP(MAX)
) is 3.3 V, the COMP pin bias voltage (V
BIAS
)
is 1.2V, and the current balancing amplifier gain (A
D
) is 5.
Using V
R
of 0.765V, and R
DS(MAX)
of 5.95m
Ω
(low-side
ON-resistance at 125°C), we find a per-phase limit of 40.44A.
(
)
CC
CC
GSF
SF
GMF
MF
SW
×
DRV
P
V
I
Q
n
Q
n
n
f
×
+
×
+
×
×
=
2
(18)
R
DS
D
R
×
R
C
R
A
L
A
R
×
×
×
=
3
(19)
Ω
=
×
Ω
×
×
×
95
=
k
pF
m
nH
R
R
291
5
.
5
3
650
2
(
×
)
SW
R
R
VID
R
R
R
f
C
V
D
A
V
×
×
×
=
1
(20)
(
)
228
V
kHz
pF
k
V
V
R
765
.
5
301
5
×
125
.
1
2
=
×
×
Ω
×
=
(
)
R
×
×
×
×
×
f
=
O
X
SW
R
RT
C
n
D
n
V
1
V
2
1
(21)
O
LIM
LIM
R
LIM
I
LIM
V
A
R
×
×
=
(22)
2
)
(
)
R
(
R
MAX
DS
D
BIAS
R
MAX
COMP
V
PHLIM
I
A
V
V
I
×
(23)
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