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參數資料
| 型號： | FAN5026MTCX |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 穩壓器 |
| 英文描述： | Dual DDR/Dual-output PWM Controller |
| 中文描述： | DUAL SWITCHING CONTROLLER, 345 kHz SWITCHING FREQ-MAX, PDSO28 |
| 封裝： | 4.40 MM, MO-153AB, TSSOP-28 |
| 文件頁數： | 11/17頁 |
| 文件大小： | 192K |
| 代理商： | FAN5026MTCX |
FAN5026
PRODUCT SPECIFICATION
REV. 1.0.2b 9/2/03
11
Setting the Current Limit
A ratio of ISNS is also compared to the current established
when a 0.9 V internal reference drives the ILIM pin.
The threshold is determined at the point when the
9
3
. Since
therefore
,
Since the tolerance on the current limit is largely dependent
on the ratio of the external resistors it is fairly accurate if the
voltage drop on the Switching Node side of R
SENSE
is an
accurate representation of the load current. When using the
MOSFET as the sensing element, the variation of R
DS(ON)
causes proportional variation in the ISNS. This value not
only varies from device to device, but also has a typical
junction temperature coefficient of about 0.4%/°C (consult
the MOSFET datasheet for actual values), so the actual
current limit set point will decrease proportional to increas-
ing MOSFET die temperature. A factor of 1.6 in the current
limit setpoint should compensate for all MOSFET R
DS(ON)
variations, assuming the MOSFET’s heat sinking will keep
its operating die temperature below 125°C.
Figure 11. Improving Current Sensing Accuracy
More accurate sensing can be achieved by using a resistor
(R1) instead of the R
DS(ON)
of the FET as shown in Figure
11. This approach causes higher losses, but yields greater
accuracy in both V
DROOP
and I
LIMIT
. R1 is a low value
(e.g. 10m
) resistor.
Current limit (I
LIMIT
) should be set sufficiently high as to
allow inductor current to rise in response to an output load
transient. Typically, a factor of 1.3 is sufficient. In addition,
since I
LIMIT
is a peak current cut-off value, we will need to
multiply I
LOAD(MAX)
by the inductor ripple current (we'll
use 25%). For example, in Figure 5 the target for I
LIMIT
would be:
I
LIMIT
> 1.2
×
1.25
×
1.6
×
6A
≈
14A
(4)
Gate Driver Section
The Adaptive gate control logic translates the internal PWM
control signal into the MOSFET gate drive signals providing
necessary amplification, level shifting and shoot-through
protection. Also, it has functions that help optimize the IC
performance over a wide range of operating conditions.
Since MOSFET switching time can vary dramatically from
type to type and with the input voltage, the gate control logic
provides adaptive dead time by monitoring the gate-to-
source voltages of both upper and lower MOSFETs. The
lower MOSFET drive is not turned on until the gate-to-
source voltage of the upper MOSFET has decreased to less
than approximately 1 volt. Similarly, the upper MOSFET is
not turned on until the gate-to-source voltage of the lower
MOSFET has decreased to less than approximately 1 volt.
This allows a wide variety of upper and lower MOSFETs to
be used without a concern for simultaneous conduction, or
shoot-through.
There must be a low-resistance, low-inductance path
between the driver pin and the MOSFET gate for the adap-
tive dead-time circuit to work properly. Any delay along that
path will subtract from the delay generated by the adaptive
dead-time circuit and shoot-through may occur.
Frequency Loop Compensation
Due to the implemented current mode control, the modulator
has a single pole response with -1 slope at frequency deter-
mined by load
where R
O
is load resistance, C
O
is load capacitance. For this
type of modulator, Type 2 compensation circuit is usually
sufficient. To reduce the number of external components and
simplify the design task, the PWM controller has an inter-
nally compensated error amplifier. Figure 12 shows a Type 2
amplifier and its response along with the responses of a
current mode modulator and of the converter. The Type 2
amplifier, in addition to the pole at the origin, has a zero-pole
pair that causes a flat gain region at frequencies between the
zero and the pole.
This region is also associated with phase ‘bump’ or reduced
phase shift. The amount of phase shift reduction depends the
width of the region of flat gain and has a maximum value of
90 degrees. To further simplify the converter compensation,
the modulator gain is kept independent of the input voltage
variation by providing feed-forward of VIN to the oscillator
ramp.
ISNS
ILIM
4
×
>
ISNS
I
R
DS ON
R
SENSE
)
×
+
---100
=
I
LIMIT
R
ILIM
0.9V
4
3
×
9
----------------------+
100
R
DS ON
SENSE
)
)
×
=
(3a)
or
R
ILIM
I
LIMIT
---11.2
100
-------------+
R
R
DS ON
(
)
)
×
=
(3b)
LDRV
PGND
ISNS
R
SENSE
R
Q2
F
PO
2
R
O
C
O
----------1
=
(5)
F
Z
π
R
2
C
1
2
6kHz
=
=
(6a)
F
P
2
R
2
C
2
-------1
600kHz
=
=
(6b)
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