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參數(shù)資料
| 型號： | FAN5069EMTCX |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 15/22頁 |
| 文件大小： | 622K |
| 描述： | IC REG DL BCK/LINEAR 16TSSOP |
| 產(chǎn)品變化通告： | Metallization Mask Rev 18/Apr/2007 |
| 標準包裝： | 2,500 |
| 拓撲： | 降壓（降壓）同步（1），線性（LDO）（1） |
| 功能： | 任何功能 |
| 輸出數(shù)： | 2 |
| 頻率 - 開關(guān)： | 200kHz |
| 電壓/電流 - 輸出 1： | 控制器 |
| 電壓/電流 - 輸出 2： | 控制器 |
| 帶 LED 驅(qū)動器： | 無 |
| 帶監(jiān)控器： | 無 |
| 帶序列發(fā)生器： | 無 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | * |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | * |
| 包裝： | 帶卷 (TR) |
?2005 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN5069 Rev. 1.1.5
15
P
GATE
is determined by the following equation:
(EQ. 14)
where Q
G
is the total gate charge to reach V
CC
.
Low-Side Losses
Q2 switches on or off with its parallel schottky diode
simultaneously conducting, so the V
DS
H 0.5V. Since
P
SW
is proportional to V
DS
, Q2's switching losses are
negligible and Q2 is selected based on R
DS(ON)
alone.
Conduction losses for Q2 are given by the equation:
(EQ. 15)
where R
DS(ON)
is the R
DS(ON)
of the MOSFET at the
highest operating junction temperature and D=V
OUT
/V
IN
is the minimum duty cycle for the converter.
Since D
MIN
< 20% for portable computers, (1-D) H 1 pro-
duces a conservative result, simplifying the calculation.
The maximum power dissipation (P
D(MAX)
) is a function
of the maximum allowable die temperature of the low-
side MOSFET, the ?/DIV>
JA,
and the maximum allowable
ambient temperature rise. P
D(MAX)
is calculated using
the following equation:
(EQ. 16)
?/DIV>
JA
depends primarily on the amount of PCB area
devoted to heat sinking.
Selection of MOSFET Snubber Circuit
The Switch node (SW) ringing is caused by fast switch-
ing transitions due to the energy stored in the parasitic
elements. This ringing on the SW node couples to other
circuits around the converter if they are not handled
properly. To dampen this ringing, an R-C snubber is con-
nected across the SW node and the source of the low-
side MOSFET.
R-C components for the snubber are selected as follows:
a) Measure the SW node ringing frequency (F
ring
) with a
low capacitance scope probe.
b) Connect a capacitor (C
SNUB
) from SW node to GND
so that it reduces this ringing by half.
c) Place a resistor (R
SNUB
) in series with this capacitor.
R
SNUB
is calculated using the following equation:
(EQ. 17)
d) Calculate the power dissipated in the snubber resistor
as shown in the following equation:
(EQ. 18)
where, V
IN(MAX)
is the maximum input voltage and FSW
is the converter switching frequency.
The snubber resistor chosen should be de-rated to han-
dle the worst-case power dissipation. Do not use wire-
wound resistors for R
SNUB
.
Loop Compensation
Typically, the closed loop crossover frequency (F
cross
),
where the overall gain is unity, should be selected to
achieve optimal transient and steady-state response to
disturbances in line and load conditions. It is recom-
mended to keep F
cross
below fifth of the switching fre-
quency of the converter. Higher phase margin tends to
have a more stable system with more sluggish response
to load transients. Optimum phase margin is about 60? a
good compromise between steady state and transient
responses. A typical design should address variations
over a wide range of load conditions and over a large
sample of devices.
P
Gate
Q
G
V
CC
F
SW
?/DIV>
?/DIV>
=
P
COND
1 D
(
) I
OUT
2
?/DIV>
R
DS ON
( )
?/DIV>
=
P
D MAX
(
)
T
J MAX
(
)
T
A MAX
(
)
?/DIV>
JA
-------------- ----------------- ----------------- -
=
R
SNUB
2
?nbsp F
ring
C
SNUB
?/DIV>
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?/DIV>
--------- ----------------- ----------------- --- -
=
P
R SNUB
(
)
C
SNUB
V
IN MAX
(
)
2
F
SW
?/DIV>
?/DIV>
=
Figure 24. Closed-Loop System with Type-3 Network
PWM
&
DRIVER
Summing
Amplifier
?/DIV>
Ramp
Generator
Current
Sense
Amplifier
Q1
Q2
V
OUT
L
V
IN
C
R
DC
R
ES
R
L
C2
R3
C3
C1
R2
R1
R
RAMP
V
IN
Reference
R
BIAS
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