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參數資料
| 型號： | FAN5070 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | High Performance Programmable Synchronous DC-DC Controller |
| 中文描述： | 高性能可編程同步DC - DC控制器 |
| 文件頁數： | 9/14頁 |
| 文件大小： | 147K |
| 代理商： | FAN5070 |
FAN5070
REV. 1.0.1 8/7/01
9
Design Considerations and Component
Selection
Additional information on design and component selection
may be found in Fairchild’s Application Note 57.
MOSFET Selection
This application requires N-channel Logic Level Enhance-
ment Mode Field Effect Transistors. Desired characteristics
are as follows:
Low Static Drain-Source On-Resistance, R
DS,ON
< 20m
(lower is better)
Low gate drive voltage, V
GS
= 4.5V rated
Power package with low Thermal Resistance
Drain-Source voltage rating > 15V.
The on-resistance (R
DS,ON
) is the primary parameter for
MOSFET selection. The on-resistance determines the power
dissipation within the MOSFET and therefore significantly
affects the efficiency of the DC-DC Converter. For details
and a spreadsheet on MOSFET selection, refer to Applica-
tions Bulletin AB-8.
Inductor Selection
Choosing the value of the inductor is a trade-off between
allowable ripple voltage and required transient response. The
system designer can choose any value within the allowed
minimum to maximum range in order to either minimize rip-
ple or maximize transient performance. The first order equa-
tion (close approximation) for minimum inductance is:
where:
V
in
= Input Power Supply
V
out
= Output Voltage
f = DC/DC converter switching frequency
ESR = Equivalent series resistance of all output capacitors in
parallel
V
ripple
= Maximum peak to peak output ripple voltage budget.
The first order equation for maximum allowed inductance is:
where:
C
o
= The total output capacitance
I
pp
= Maximum to minimum load transient current
V
tb
= The output voltage tolerance budget allocated to load
transient
D
m
= Maximum duty cycle for the DC/DC converter (usu-
ally 95%).
Some margin should be maintained away from both L
min
and
L
max
. Adding margin by increasing L almost always adds
expense since all the variables are predetermined by system
performance except for C
o
, which must be increased to
increase L. Adding margin by decreasing L can be done by
purchasing capacitors with lower ESR. The FAN5070 pro-
vides significant cost savings for the newer CPU systems
that typically run at high supply current.
FAN5070 Short Circuit Current Characteristics
The FAN5070 protects against output short circuit on the
core supply by latching off both the high-side and low-side
MOSFETs. The FAN5070 short circuit current characteristic
includes a hysteresis function that prevents the DC-DC con-
verter from oscillating in the event of a short circuit. The
short circuit limit is set with the R
S
resistor, as given by the
formula
with I
Detect
≈
50μA, ISC the desired current limit, and R
DS,on
the high-side MOSFET’s on resistance. Remember to make
the R
S
large enough to include the effects of initial tolerance
and temperature variation on the MOSFET’s R
DS,on
. Alter-
nately, use of a sense resistor in series with the source of the
MOSFET, as shown in Figure 6, eliminates this source of
inaccuracy in the current limit.
As an example, Figure 3 shows the typical characteristic of
the DC-DC converter circuit with two FDD6690A high-side
MOSFETs (R
DS
= 17m
maximum at 25°C * 1.25 at 75°C
= 21.25m
each for a total of 10.6m
) and a 6.19K
R
S
.
Figure 3. FAN5070 Short Circuit Characteristic
The converter exhibits a normal load regulation characteris-
tic until the voltage across the MOSFET exceeds the internal
short circuit threshold of 50μA * 6.2K
= 310mV, which
occurs at 310mV/10.6m
= 29A. [Note that this current
limit level can be as high as 310mV/6.5m
= 48A, if the
MOSFET has typical R
DS,on
rather than maximum, and is at
25°C. This is the reason for using the external sense resistor.]
At this point, the internal comparator trips and signals the
L
min
(Vin
–
V
out
)
f
x
V
out
V
in
x
ESR
V
ripple
=
L
max
(Vin
–
V
out
) D
m
V
tb
I
pp2
= 2C
O
R
S
I
SC
*R
DS, on
I
Detect
=
V
O
(
0 10 20 30 40 50
Output Current (A)
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