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參數資料
| 型號： | FAN5236QSCX |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 穩壓器 |
| 英文描述： | Dual Mobile-Friendly DDR / Dual-output PWM Controller |
| 中文描述： | DUAL SWITCHING CONTROLLER, 345 kHz SWITCHING FREQ-MAX, PDSO28 |
| 封裝： | QSOP-28 |
| 文件頁數： | 13/20頁 |
| 文件大小： | 199K |
| 代理商： | FAN5236QSCX |
FAN5236
PRODUCT SPECIFICATION
REV. 1.1.7 4/4/03
13
The lower MOSFET drive is not turned on until the gate-to-
source voltage of the upper MOSFET has decreased to less
than approximately 1 volt. Similarly, the upper MOSFET is
not turned on until the gate-to-source voltage of the lower
MOSFET has decreased to less than approximately 1 volt.
This allows a wide variety of upper and lower MOSFETs to
be used without a concern for simultaneous conduction, or
shoot-through.
There must be a low-resistance, low-inductance path
between the driver pin and the MOSFET gate for the adap-
tive dead-time circuit to work properly. Any delay along that
path will subtract from the delay generated by the adaptive
dead-time circit and shoot-through may occur.
Frequency Loop Compensation
Due to the implemented current mode control, the modulator
has a single pole response with -1 slope at frequency deter-
mined by load
where R
O
is load resistance, C
O
is load capacitance.
For this type of modulator, Type 2 compensation circuit is
usually sufficient. To reduce the number of external compo-
nents and simplify the design task, the PWM controller has
an internally compensated error amplifier. Figure 13 shows a
Type 2 amplifier and its response along with the responses of
a current mode modulator and of the converter. The Type 2
amplifier, in addition to the pole at the origin, has a zero-pole
pair that causes a flat gain region at frequencies between the
zero and the pole.
This region is also associated with phase ‘bump’ or reduced
phase shift. The amount of phase shift reduction depends the
width of the region of flat gain and has a maximum value of
90 degrees. To further simplify the converter compensation,
the modulator gain is kept independent of the input voltage
variation by providing feed-forward of VIN to the oscillator
ramp.
The zero frequency, the amplifier high frequency gain and
the modulator gain are chosen to satisfy most typical appli-
cations. The crossover frequency will appear at the point
where the modulator attenuation equals the amplifier high
frequency gain. The only task that the system designer has to
complete is to specify the output filter capacitors to position
the load main pole somewhere within one decade lower than
the amplifier zero frequency. With this type of compensation
plenty of phase margin is easily achieved due to zero-pole
pair phase ‘boost’.
Figure 13. Compensation
Conditional stability may occur only when the main load
pole is positioned too much to the left side on the frequency
axis due to excessive output filter capacitance. In this case,
the ESR zero placed within the 10kHz...50kHz range gives
some additional phase ‘boost’. Fortunately, there is an oppo-
site trend in mobile applications to keep the output capacitor
as small as possible.
If a larger inductor value or low ESR values are called for by
the application, additional phase margin can be achieved by
putting a zero at the LC crossover frequency. This can be
achieved with a capacitor across across the feedback resistor
(e.g. R5 from Figure 5) as shown below.
Figure 14. Improving Phase Margin
The optimal value of C(Z) is:
Protection
The converter output is monitored and protected against
extreme overload, short circuit, over-voltage and under-
voltage conditions.
A sustained overload on an output sets the PGx pin low and
latches-off the whole chip. Operation can be restored by
cycling the VCC voltage or by toggling the EN pin.
F
PO
2
R
O
C
O
--------1
=
(7)
F
Z
2
R
2
C
1
---------1
6kHz
=
=
(8a)
F
P
2
R
2
C
2
---------1
600kHz
=
=
(8b)
R1
R2
EA Out
C1
C2
REF
V
IN
Convete
0
14
18
modulator
F
P0
F
Z
F
P
error amp
C(OUT)
VOUT
C(Z)
R5
VSEN
L(OUT)
R6
C Z
----L OUT
)
R5
C OUT
)
×
=
(9)
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