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參數資料
| 型號： | FAN7930BM |
| 廠商： | Fairchild Semiconductor |
| 文件頁數： | 11/22頁 |
| 文件大小： | 1849K |
| 描述： | IC PFC CTLR CRITICAL CONF 8-SOIC |
| 標準包裝： | 95 |
| 模式： | 臨界傳導（CRM） |
| 頻率 - 開關： | 250kHz ~ 350kHz |
| 電流 - 啟動： | 120µA |
| 電源電壓： | 13 V ~ 20 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 8-SOP |
| 包裝： | 管件 |
?2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN7930B " Rev. 1.0.3
11
Applications Information
1. Startup: Normally, supply voltage (V
CC
) of a PFC
block is fed from the additional power supply, which can
be called standby power. Without this standby power,
auxiliary winding for zero current detection can be used
as a supply source. Once the supply voltage of the PFC
block exceeds 12 V, internal operation is enabled until
the voltage drops to 8.5 V. If V
CC
exceeds V
Z
, 20 mA
current is sinking from V
CC
.
V
CC
V
Z
+
-
V
T H ( S / S )
12
8 . 5
V
C C
2 .5 V R E F
in te r n a l
b ia s
V
B I A S
V
R E F
r e s e t
H : o p e n
2 0 m A
P F C In d u c to r
A u x . W in d in g
V
I N
P F C
V
O U T
P F C
E x te r n a l V
C C
c ir c u it
w h e n n o s ta n d b y p o w e r e x is ts .
8
Figure 22. Startup Circuit
2. INV Block: Scaled-down voltage from the output is
the input for the INV pin. Many functions are embedded
based on the INV pin: transconductance amplifier,
output OVP comparator, and disable comparator.
For the output voltage control, a transconductance
amplifier is used instead of the conventional voltage
amplifier. The transconductance amplifier (voltage-
controlled current source) aids the implementation of
the OVP and disable functions. The output current of
the amplifier changes according to the voltage
difference of the inverting and non-inverting input of
the amplifier. To cancel down the line input voltage
effect on power factor correction, the effective control
response of the PFC block should be slower than the
line frequency and this conflicts with the transient
response of the controller. Two-pole one-zero type
compensation can meet both requirements.
The OVP comparator shuts down the output drive
block when the voltage of the INV pin is higher than
2.675 V and there is 0.175 V hysteresis. The disable
comparator disables operation when the voltage of the
inverting input is lower than 0.35 V and there is
100 mV hysteresis. An external small-signal MOSFET
can be used to disable the IC, as shown in Figure 23.
The IC operating current decreases to reduce power
consumption if the IC is disabled. Figure 24 is the
timing chart of the internal circuit near the INV pin
when rated PFC output voltage is 390 VDC and VCC
supply voltage is 15 V.
Figure 23. Circuit Around INV Pin
Figure 24. Timing Chart for INV Block
3. OVP Pin: Over-Voltage Protection (OVP) is
embedded by the information at the INV pin. That
information comes from the output through the voltage
dividing resistors. To scale down from a high voltage to
a low one, high resistance is normally used with low
resistance. If the resistor of high resistance gets
damaged and resistance is changed to high, though INV
pin information is normal, output voltage exceeds its
rated output. If this occurs, the output electrolytic
capacitor may be damaged. To prevent such a
catastrophe additional OVP pin is assigned to double-
check output voltage. Additional OVP may be called
second OVP, while INV pin OVP is called first OVP.
Since the two OVP conditions are quite different, the
protection recovering mode is different.
VP
V
MP
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