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參數(shù)資料
| 型號： | FDMS2380 |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 外設及接口 |
| 英文描述： | 740; 38000/740 Series; Microcontroller; Bit Size: 8-bit; ROM: 2K; RAM: 192; ROM Type: QzROM; CPU: 740 core; Minimum Instruction Execution Time (ns): 250 (@8MHz); Operating Frequency / Supply Voltage: 1.8 to 5.5V; Operating Ambient Temperature (°C): -20 to 85; Package Code: PLSP0020JB-A (20P2F-A) |
| 中文描述： | HALF BRIDGE BASED PRPHL DRVR, QCC18 |
| 封裝： | QFN-18 |
| 文件頁數(shù)： | 6/15頁 |
| 文件大小： | 388K |
| 代理商： | FDMS2380 |
F
FDMS2380 Rev. A
www.fairchildsemi.com
6
Overvoltage
(see figure 4) While in the Excitation mode if
the V
BATT
pin rises above the over-voltage threshold,
V
BATT(ov)
, the FDMS2380 is forced into the Recirculation
mode and a protection fault signal on the diagnostic pin
DIAG is generated. This condition is not reset by INA going
low but by the voltage of the V
BATT
pin returning below the
V
BATT(ov)
level. A protection fault pulse will be issued each
time the device is driven into the Excitation state while the
over-voltage condition exists.
The FDMS2380 is designed with a fast responding over-
voltage circuit that disables the output slope control circuit
which minimizes radiated EMI. However, voltage transitions
on the V
BATT
pin which exceed 30 volts above the battery
need to be limited to a rise time no faster then 2.2 V/
μ
s
through the use of a power supply bypass capacitor.
Undervoltage
(see figure 6) The FDMS2380 will operate
down to a minimum voltage of V
BATT(uv)
. If the battery supply
drops below this minimum voltage the device is forced into
the Standby mode. If INA is high during this condition a 2
μ
s
to 10
μ
s protection fault pulse is issued on the diagnostic
DIAG pin. In addition, a diagnostic pulse will be generated
each time INA transitions from a low to a high logic level
while remaining in this under-voltage condition.
The FDMS2380 will return to normal operation when V
BATT
is 6 volts or greater.
Diagnostic Functions
Open Load Detect
(see figure 5) While INA and INB are
high, if the load current fails to rise above the open load
current level, I
OUT(ol)
, before INB transitions low an open
load diagnostic fault will be issued. The diagnostic pin will
be driven low on the falling edge of the INB signal and
remain low until INA is returned to a logic 0 condition. The
open load detect mechanism senses current flowing through
the NDMOS at the falling edge of the INB signal. If an open
load condition exists during the Excitation phase but is
corrected before the INB falling edge the open load
condition would not be detected and the open load
diagnostic fault would not be generated.
The open load detection circuit does not alter the operation
of the FDMS2380 and the PDMOS and NDMOS output
transistors will be driven into the operational modes as
commanded by the INA and INB inputs.
If during the detection of the open load condition a protection
fault condition also arises, the open load diagnostics will be
terminated and then after a 2
μ
s to 10
μ
s blanking period the
protection diagnostic will be generated.
Operational Truth Table
Conditions
H = High, L = Low, X = Don’t Care
General operation INA and INB are standard logic inputs that control Standby, Excitation, Recirculation, Diagnostics, and
Fast turn-off modes in the FDMS2380.
INA
INB
NDMOS
PDMOS
Standby Mode:
L
L
OFF
OFF
Soft Short Test Mode
L
H
OFF
ON
Excitation Mode: (No protection faults)
H
H
ON
ON
Recirculation Mode
H
L
OFF
ON
Fast Turn-off Mode: V
FB
< V
OUT
< V
OUT(cl1
)
L
L
OFF
V
OUT
clamped
to V
OUT(cl2)
Alternator Load Dump: V
OUT
> V
OUT(cl1)
L
X
NDMOS in UIS
operation
NA
Thermal Shutdown: T
J
> T
J(tsd)
Current Trip: I
OUT
> I
OUT(trip)
Overvoltage: V
BATT
> V
BATT(ov)
Undervoltage: V
BATT
< V
BATT(uv)
Open Load: I
OUT
< I
OUT(ol)
refer to Open Load waveforms
(Figure 5)
H
X
OFF
ON
H
H
OFF
ON
H
H
OFF
ON
H
X
OFF
OFF
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