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參數資料
| 型號： | FM3540SMT14 |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 標準邏輯 |
| 英文描述： | 4/5 Bit Multiplexed, 1 Bit Latched Port with Standard 2-Wire Bus Interface and Non-Volatile Latches |
| 中文描述： | SPECIALTY LOGIC CIRCUIT, PDSO14 |
| 封裝： | TSSOP-14 |
| 文件頁數： | 4/10頁 |
| 文件大小： | 100K |
| 代理商： | FM3540SMT14 |
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FM3540/60 Rev. C
Multiplexer Logic
The output multiplexer logic determines what value is actually
output to the Y-port. The value that is output is dependent upon b7-
b6 of the SOPRA and SOPRB registers, as well as the external
mux_sel and override# inputs. The is only one set of MXS bits in
the SOPRA and SOPRB registers. Regardless of whether one
writes to SOPRA or SOPRB register for setting the MXS bits, the
result is the same. These same bits appear in both the registers.
If the mux_sel is logic 0 and OVRD is logic 1, then, if b7,b6 is “10”
then the value on the I-port is passed. When b7 is “00” the value
of the SOPRA register is passed on the next IIC stop condition,
and .When b7 is “01” the value of the SOPRB register is passed
on the next IIC stop condition. If mux_sel is logic 1 and OVRD is
logic 1, the input lines I0-4 are used to drive the outputs. The above
table describes all the combinations.
IIC Interface
The IIC Interface is a standard slave interface. As a slave interface
the device will not generate its own clock. Data can be read from
and written into the device. Commands for reading and writing the
registers are generated by the IIC
Master.
START and STOP Conditions
If so desired only the SOPRA register can be read. This is
accomplished by issuing a stop command after acknowledge bit
for the first byte read. If no stop is issued, the device will output the
registers in the above sequence.
Writing to the Registers
Data is written to the SOPR registers through the serial port
interface. When a write request is received with the Start Address
it is assumed that the intent is to write the SOPR registers. The
value placed in the least 6 significant bits of the register contain the
new code to be placed in the SOPR A/B registers. The value of the
two most significant bits must contain the address of the destina-
tion register SOPRA or SOPRB.
The internal non-volatile latch takes about 10 ms to update its
data. The new data is reflected on the outputs after the internal
non-volatile latch is updated, if the corresponding select bits
(MXSx, OVRD and mux_sel) are set to reflect the state of the non-
volatile register
Register Read Sequence
Slave
Address
SOPRA
SOPRB
PIPR
S
R A Register A Register A Register A P
S
1001110
1
A 00bbbbbb
A 00bbbbbb
A 00bbbbbb
A
P
Register Write Sequence
Slave
Address W A Register A S
SOPRx
S
S
1001110
0
A xxbbbbbb
A
S
xx = Register Selection bits (MXSB and MXSA) xx = 00 selects
SOPRA, 01 selects SOPRB
Register Write Sequence using
Repeated Start Condition
Slave
SOPRA
Register
Slave
SOPRx
Register
S Address R A
A S Address W A
A P
S 1001110 1
A 00bbbbbb A
S 1001110 0
A xxbbbbbb A
P
Figure 4
The IIC protocol uniquely defines START and STOP conditions.
A START condition is defined as a HIGH to LOW transition of the
SDA signal while SCL is HIGH. A STOP condition is defined as a
LOW to HIGH transition of the SDA signal while SCL is HIGH.
These are shown in Figure 2.
Device Addressing
The device uses 7 bit IIC addressing. The address has been
defined as 1001 110 if the ASEL input is ‘1’ and 0110 111 if the
ASEL input is ‘0’. The address byte is the first byte of data sent after
a start condition. This is the only address that this device will
respond to. The device will not respond to the general call address
0000 000.
Reading from the Registers
Data can be read from both of the internal registers. All reads are
non-destructive and do not change the value in the register or the
internal state of the device. When a start condition is received with
a read request both registers can be read out in the following
sequence.
(1)
SOPRA - Serial Output Port Register A
(2)
SPORB - Serial Output Port Register B
(3)
PIPR - PORT-I Value
SDA
SCL
START
Condition
STOP
Condition
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