
FM8P51
Rev1.2 Mar 15, 2005
P.14/FM8P51
FEELING
TECHNOLOGY
= 1, A new byte is received while the SPIRCB register is still holding the previous data. In this case, the data
in SPISR register will be ignored and lost.
= 0, Not overflow.
SPION
: SPI module enable bit
= 1, Enable SPI module.
= 0, Disable SPI module.
CKEDG
: Clock edge select bit
= 1, Data shifts out on falling edge of SCK, and shifts in on rising edge of SCK.
= 0, Data shifts in on rising edge of SCK, and shifts in on falling edge of SCK.
2.1.11 TMR1 (Timer 1 Register) (Bank 0)
Address
Name
B7
B6
0Eh (r/w)
TMR1
TMR17
TMR16
TMR17:TMR10
: Timer 1 register and increase until the value matches to PR1 register, and then reset to “0”.
2.1.12 PR1 (Timer 1 Pulse-width Register) (Bank 0)
Address
Name
B7
B6
B5
0Fh (r/w)
PR1
PR17
PR16
PR15
PR17:PR10
: Timer 1 period register.
2.1.13 T23CON (Timer 2&3 Control Register) (Bank 1)
Address
Name
B7
B6
B5
0Ah (r/w)
T23CON
-
-
-
T2CS
: Timer 2 clock source selection bit
= 1, External clock input T23CKI pin.
= 0, Internal clock Fosc/4.
T2ON
: Timer 2 module enable bit
= 1, Enable Timer 2 module.
= 0, Disable Timer 2 module.
T3CS
: Timer 3 clock source selection bit
= 1, External clock input T23CKI pin.
= 0, Internal clock Fosc/4.
T3ON
: Timer 3 module enable bit
= 1, Enable Timer 3 module.
= 0, Disable Timer 3 module.
T16
:
8-bit or 16-bit timer selection bit for Timer2 & Timer3
= 1, Timer2 & Timer3 are concatenated to form a 16-bit timer.
= 0, Timer2 & Timer3 are two 8-bit incrementing timers.
Bit7:BIT5
: Not used. Read as “0”s
B5
B4
B3
B2
B1
B0
TMR15
TMR14
TMR13
TMR12
TMR11
TMR10
B4
PR14
B3
PR13
B2
PR12
B1
PR11
B0
PR10
B4
T16
B3
T3ON
B2
T3CS
B1
T2ON
B0
T2CS