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參數(shù)資料
| 型號： | FM8P51E |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | EPROM/ROM-Based 8-Bit Microcontroller |
| 中文描述： | 存儲器/基于ROM的8位微控制器 |
| 文件頁數(shù)： | 33/60頁 |
| 文件大小： | 369K |
| 代理商： | FM8P51E |
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FM8P51
Rev1.2 Mar 15, 2005
P.33/FM8P51
FEELING
TECHNOLOGY
2.8 Interrupts
The FM8P51 series has up to eight sources of interrupt:
1. External interrupt INT pin.
2. TMR0 overflow interrupt.
3. TMR1 match interrupt.
4. TMR2 match interrupt.
5. TMR3 match interrupt.
6. SPI receive module interrupt.
7. SPI transmit module interrupt.
8. RFC module interrupt.
INTFLAG is the interrupt flag register that recodes the interrupt requests in the relative flags.
A global interrupt enable bit, GIE (OPTION<6>), enables (if set) all un-masked interrupts or disables (if cleared) all
interrupts. Individual interrupts can be enabled/disabled through their corresponding enable bits in INTEN register
regardless of the status of the GIE bit.
When an interrupt event occur with the GIE bit and its corresponding interrupt enable bit are all set, the GIE bit will
be cleared by hardware to disable any further interrupts, and the next instruction will be fetched from address 001h.
The interrupt flag bits must be cleared by software before re-enabling GIE bit to avoid recursive interrupts.
Executing the ENI instruction will set the GIE bit, and executing the DISI instruction will clear the GIE bit.
The RETFIE instruction exits the interrupt routine and set the GIE bit to re-enable interrupt.
The flag bit in INTFLAG register is set by interrupt event regardless of the status of its mask bit. Reading the
INTFLAG register will be the logic AND of INTFLAG and INTEN.
When an interrupt is generated by the INT instruction, the next instruction will be fetched from address 002h.
2.8.1 External INT Interrupt
External interrupt on INT pin is rising or falling edge triggered selected by INTEDG (OPTION<6>).
When a valid edge appears on the INT pin the flag bit INTIF (INTFLAG<1>) is set. This interrupt can be disables by
clearing INTIE bit (INTEN<1>).
The INT0 pin interrupt can wake-up the system from SLEEP condition, if bit INT0IE was set before going to SLEEP.
If GIE bit was set, the program will execute interrupt service routine after wake-up; or if GIE bit was cleared, the
program will execute next PC after wake-up.
2.8.2 Timer0 Interrupt
An overflow (FFh
00h) in the TMR0 register will set the flag bit T0IF (INTFLAG<0>).
This interrupt can be disabled by clearing T0IE bit (INTEN<0>).
2.8.3 Timer1 Interrupt
An match condition (TMR1 = PR1) in the TMR1 register will set the flag bits T1IF (INTFLAG<3>) and TM1IF
(SPISTAT<4>).
If user wants to clear the T1IF bit, user needs to clear the TM1IF bit first, and then the T1IF bit can be cleared by
software.
This interrupt can be disabled by clearing T1IE bit (INTEN<3>).
2.8.4 Timer2 Interrupt
In 8-bit mode, an match condition (TMR2 = PR2) in the TMR2 register will set the flag bit T2IF (INTFLAG<4>).
In 16-bit mode, an match condition (TMR3:TMR2 = PR3:PR2) in the TMR3 and TMR2 register will set the flag bit
T2IF (INTFLAG<4>).
This interrupt can be disabled by clearing T2IE bit (INTEN<4>).
相關(guān)PDF資料 |
PDF描述 |
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| FM8P54 | EPROM/ROM-Based 8-Bit Microcontroller Series |
| FM8P54E | EPROM/ROM-Based 8-Bit Microcontroller Series |
| FM8P56 | EPROM/ROM-Based 8-Bit Microcontroller Series |
| FM8P56E | EPROM/ROM-Based 8-Bit Microcontroller Series |
| FM93C06 | 256-Bit Serial CMOS EEPROM(256位的串行CMOS EEPROM) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FM8P51EF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EPROM/ROM-Based 8-Bit Microcontroller |
| FM8P51EP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EPROM/ROM-Based 8-Bit Microcontroller |
| FM8P51F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EPROM/ROM-Based 8-Bit Microcontroller |
| FM8P51P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EPROM/ROM-Based 8-Bit Microcontroller |
| FM8P54 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EPROM/ROM-Based 8-Bit Microcontroller Series |
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