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參數資料
| 型號： | FM93CS06 |
| 廠商： | Fairchild Semiconductor Corporation |
| 元件分類： | DRAM |
| 英文描述： | 256-Bit Serial CMOS EEPROM With Data Protect and Sequential Read(帶連續讀操作和數據保護的256位串行CMOS EEPROM) |
| 中文描述： | 256位串行CMOS EEPROM，帶有數據保護和連續讀（帶連續讀操作和數據保護的256位串行EEPROM中的CMOS） |
| 文件頁數： | 4/16頁 |
| 文件大小： | 172K |
| 代理商： | FM93CS06 |
4
www.fairchildsemi.com
FM93CS06 Rev. C.1
F
w
Absolute Maximum Ratings
(Note 1)
Ambient Storage Temperature
All Input or Output Voltages
with Respect to Ground
Lead Temperature
(Soldering, 10 sec.)
ESD rating
DC and AC Electrical Characteristics
V
CC
= 2.7V to 4.5V unless otherwise specified. Refer to
page 3 for V
CC
= 4.5V to 5.5V.
-65
°
C to +150
°
C
+6.5V to -0.3V
+300
°
C
2000V
Operating Conditions
Ambient Operating Temperature
FM93CS06L/LZ
FM93CS06LE/LZE
FM93CS06LV/LZV
0
°
C to +70
°
C
-40
°
C to +85
°
C
-40
°
C to +125
°
C
Power Supply (V
CC
)
2.7V to 5.5V
Symbol
Parameter
Conditions
Min
Max
Units
I
CCA
I
CCS
Operating Current
CS = V
IH
, SK= 250 KHz
CS = V
IL
1
mA
Standby Current
L
LZ (2.7V to 4.5V)
Input Leakage
Output Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
SK Clock Frequency
SK High Time
SK Low Time
10
1
±
1
μ
A
μ
A
μ
A
I
IL
I
OL
V
IL
V
IH
V
OL
V
OH
f
SK
t
SKH
t
SKL
t
CS
t
CSS
t
PRES
t
DH
t
PES
t
DIS
t
CSH
t
PEH
t
PREH
t
DIH
t
PD
t
SV
t
DF
t
WP
V
IN
= 0V to V
CC
(Note 2)
-0.1
0.8V
CC
0.15V
CC
V
CC
+1
0.1V
CC
V
I
OL
= 10
μ
A
I
OH
= -10
μ
A
(Note 3)
V
0.9V
CC
0
1
1
250
KHz
μ
s
μ
s
μ
s
μ
s
ns
ns
ns
μ
s
ns
ns
ns
μ
s
μ
s
μ
s
μ
s
ms
Minimum CS Low Time
(Note 4)
1
CS Setup Time
PRE Setup Time
DO Hold Time
PE Setup Time
DI Setup Time
0.2
50
70
50
0.4
CS Hold Time
PE Hold Time
PRE Hold Time
DI Hold Time
Output Delay
0
250
50
0.4
2
CS to Status Valid
1
CS to DO in Hi-Z
Write Cycle Time
CS = V
IL
0.4
15
Capacitance
T
A
= 25
°
C, f = 1 MHz or 250
KHz(Note 5)
Symbol
Test
Typ
Max
Units
C
OUT
C
IN
Output Capacitance
Input Capacitance
5
5
pF
pF
Note 1
:
to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect device reliability.
Stress above those listed under
“
Absolute Maximum Ratings
”
may cause permanent damage
Note 2
:
Typical leakage values are in the 20nA range.
Note 3
:
SK clock speed (minimum SK period) is determined by the interaction of several AC parameters stated
in the datasheet. Within this SK period, both t
SKH
and t
limits must be observed. Therefore, it is not
allowable to set 1/f
SK
= t
SKHminimum
+ t
SKLminimum
for shorter SK cycle time operation.
Note 4
:
CS (Chip Select) must be brought low (to V
) for an interval of t
in order to reset all internal
device registers (device reset) prior to beginning another opcode cycle. (This is shown in the opcode
diagram on the following page.)
The shortest allowable SK clock period = 1/f
(as shown under the f
parameter). Maximum
Note 5
:
This parameter is periodically sampled and not 100% tested.
AC Test Conditions
V
CC
Range
V
/V
Input Levels
0.3V/1.8V
V
/V
V
/V
Timing Level
0.8V/1.5V
I
OL
/I
OH
Timing Level
1.0V
2.7V
≤
V
≤
5.5V
(Extended Voltage Levels)
4.5V
≤
V
≤
5.5V
(TTL Levels)
±
10
μ
A
0.4V/2.4V
1.0V/2.0V
0.4V/2.4V
2.1mA/-0.4mA
Output Load: 1 TTL Gate (C
L
= 100 pF)
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