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參數資料
| 型號： | FM93CS06E |
| 廠商： | Fairchild Semiconductor Corporation |
| 元件分類： | DRAM |
| 英文描述： | (MICROWIRE⑩ Bus Interface) 256-Bit Serial EEPROM with Data Protect and Sequential Read |
| 中文描述： | （MICROWIRE的⑩總線接口），256位串行EEPROM的數據保護和連續讀 |
| 文件頁數： | 8/16頁 |
| 文件大小： | 172K |
| 代理商： | FM93CS06E |
8
www.fairchildsemi.com
FM93CS06 Rev. C.1
F
w
Input information (Start bit, Opcode and Address) for this PRDS
instruction should be issued as listed under Table1. After inputting
the last bit of address (A0 bit), CS signal must be brought low
before the next rising edge of the SK clock. This falling edge of the
CS initiates the self-timed programming cycle. It takes t
time
(Refer appropriate DC and AC Electrical Characteristics table) for
the internal programming cycle to finish. During this time, the
device remains busy and is not ready for another instruction.
Status of the internal programming can be polled as described
under WRITE instruction description. While the device is busy, it
is recommended that no new instruction be issued. The Protect
Register is permanently write-protected
at the end of this cycle.
Refer Protect Register Disablecycle diagram.
Clearing of Ready/Busy status
When programming is in progress, the Data-Out pin will display
the programming status as either BUSY (low) or READY (high)
when CS is brought high (DO output will be tri-stated when CS is
low). To restate, during programming, the CS pin may be brought
high and low any number of times to view the programming status
without affecting the programming operation. Once programming
is completed (Output in READY state), the output is
‘
cleared
’
(returned to normal tri-state condition) by clocking in a Start Bit.
After the Start Bit is clocked in, the output will return to a tri-stated
condition. When clocked in, this Start Bit can be the first bit in a
command string, or CS can be brought low again to reset all
internal circuits. Refer Clearing Ready Statusdiagram.
Related Document
Application Note: AN758 - Using Fairchild
’
s MICROWIRE
EE-
PROM.
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