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參數資料
| 型號： | FM93CS06V |
| 廠商： | Fairchild Semiconductor Corporation |
| 元件分類： | DRAM |
| 英文描述： | (MICROWIRE⑩ Bus Interface) 256-Bit Serial EEPROM with Data Protect and Sequential Read |
| 中文描述： | （MICROWIRE的⑩總線接口），256位串行EEPROM的數據保護和連續讀 |
| 文件頁數： | 11/16頁 |
| 文件大小： | 172K |
| 代理商： | FM93CS06V |
11
www.fairchildsemi.com
FM93CS06 Rev. C.1
F
w
Timing Diagrams
(Continued)
CS
SK
DI
DO
High - Z
Dummy
Bit
1
1
0
A5
A4
A1
A0
PRE
PE
0
D5
D1
D0
t
CS
PROTECT REGISTER READ CYCLE (PRREAD)
Address
Bits(6)
Start
Bit
Opcode
Bits(2)
93CS06:
Address bits pattern -> x-x-x-x-x-x; (x -> Don't Care, can be 0 or 1)
Of the 6-bit output data(D5-D0), only D3 to D0 are valid and they correspond to A3 to A0 respectively.
Address
Bits(6)
CS
PE
SK
DI
DO
High - Z
PROTECT REGISTER ENABLE CYCLE (PREN)
Start
Bit
93CS06:
Address bits pattern -> 1-1-x-x-x-x; (x -> Don't Care, can be 0 or 1)
Opcode
Bits(2)
1
0
0
A5
A4
A1
A0
PRE
t
CS
Address
Bits(6)
Data
Bits(16)
CS
PE
SK
DI
DO
93CS06:
Address bits pattern -> 0-1-x-x-x-x; (x -> Don't Care, can be 0 or 1)
Data bits pattern -> User defined
High - Z
t
CS
WRITE ALL CYCLE (WRALL)
Start
Bit
Opcode
Bits(2)
1
0
0
A5
A4
A1
A0
D15
D14
D1
D0
PRE
Busy
Ready
t
WP
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