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參數資料
| 型號： | FMS6407MTF20X |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 消費家電 |
| 英文描述： | Triple Video Drivers with Selectable HD/Progressive/SD/Bypass Filters |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO20 |
| 封裝： | LEAD FREE, TSSOP-20 |
| 文件頁數： | 13/17頁 |
| 文件大?。?/td> | 378K |
| 代理商： | FMS6407MTF20X |
REV. 1I July 2005
13
FMS6407
DATA SHEET
Power Dissipation
The FMS6407 output drive configuration must be considered
when calculating overall power dissipation. Care must be
taken not to exceed the maximum die junction temperature.
The following example can be used to calculate the
FMS4607’s power dissipation and internal temperature rise.
T
j
= T
A
+ P
d
Θ
JA
where P
d
= P
CH1
+ P
CH2
+ P
CH3
and P
CHx
= V
s
I
CH
- (V
O2
/R
L
)
where
V
O
= 2V
in
+ 0.280V
I
CH
= (I
CC
/ 3) + (V
O
/R
L
)
V
in
= RMS value of input signal
I
CC
= 105mA
V
s
= 5V
R
L
= channel load resistance
Board layout can also affect thermal characteristics. Refer to
the
Layout Considerations
Section for more information.
The FMS6407 is specified to operate with output currents
typically less than 60mA, more than sufficient for a single
(150
) video load. Internal amplifiers are current limited
to a maximum of 100mA and should withstand brief dura-
tion short circuit conditions, however this capability is not
guaranteed.
Layout Considerations
General layout and supply bypassing play major roles in
high frequency performance and thermal characteristics.
Fairchild offers a demonstration board, FMS6407DEMO, to
use as a
guide for layout and to aid in device testing and
characterization.
The FMS6407DEMO is a 4-layer board
with a full power and ground plane. For optimum results,
follow the steps below as a basis for high frequency layout:
Include 10
μ
F and 0.1
μ
F ceramic bypass capacitors
Place the 10
μ
F capacitor within 0.75 inches of the
power pin
Place the 0.1
μ
F capacitor within 0.1 inches of the
power pin
Connect all external ground pins as tightly as possible,
preferably with a large ground plane under the package
Layout channel connections to reduce mutual trace
inductance
Minimize all trace lengths to reduce series inductances.
If routing across a board, place device such that longer
traces are at the inputs rather than the outputs.
If using multiple, low impedance DC coupled outputs, special
layout techniques may be employed to help dissipate heat.
For dual-layer boards, place a 0.5” to 1” (1.27cm to 2.54cm)
square ground plane directly under the device and on the
bottom side of the board. Use multiple vias to connect the
ground planes. For multi-layer boards, additional planes
(connected with vias) can be used for additional thermal
improvements.
Worse case additional die power due to DC loading can be
estimated at (V
CC2
/4R
load
) per output channel. This assumes
a constant DC output voltage of V
CC2
. For 5V V
CC
with a
dual DC video load, add 25/(4*75) = 83mW, per channel.
A package option with an exposed DAP is available for
improved thermal performance, see
Ordering Information
on
page 16. For layout recommendations using the ePAD pack-
age , refer to the following: http://www.amkor.com/products/
notes_papers/epad.pdf
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