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參數(shù)資料
| 型號： | FMS7401LVN14 |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Digital Power Controller |
| 中文描述： | 8-BIT, EEPROM, 2.04 MHz, MICROCONTROLLER, PDIP14 |
| 封裝： | PLASTIC, DIP-14 |
| 文件頁數(shù)： | 50/80頁 |
| 文件大小： | 1535K |
| 代理商： | FMS7401LVN14 |
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PRODUCT SPECIFICATION
FMS7401/7401L
REV. 1.0.2 6/23/04
50
10.1.6 Interrupt Handling
When an interrupt is recognized, the current instruction completes its execution. The return address (the current value in the
program counter, PC) is pushed onto the stack, the global interrupt (G) mask of the status register (SR) is cleared, and execu-
tion continues at the address specified by the respective interrupt vector (see
Table 30
). This process takes five instruction
cycles to complete. The interrupt vector contains the address of the software’s interrupt service routine (ISR). Initially, the ISR
may save (if necessary) the status register’s contents. Software, however, cannot restore SR using the traditional microcontrol-
ler methods. Just before ending the ISR, software may restore the contents of SR by using only the special inherent instructions
(e.g. SC, RC and LDC) or specially defined software routines since all SR bits except for G are read only when using direct,
indirect, or indexed instructions (e.g. LD , ST, RBIT or SBIT). Upon exiting the ISR, software must clear the appropriate
triggering pending flag and execute a return-from-interrupt (RETI) instruction. The RETI instruction pulls the saved return
address off the stack in reverse order restoring PC and setting G of SR to one. Instruction execution resumes at the restored the
program counter address.
The microcontroller core is capable of supporting five interrupts. Four are maskable through G of the SR and the fifth (software
interrupt) is not inhibited by G (see
Figure 18
). The execution of the INTR instruction generates a software interrupt. Once the
INTR instruction is executed, the microcontroller core will interrupt whether G is set or not. The INTR interrupt is executed in
the same manner as the other maskable interrupts where PC is stacked and G is cleared. This means, if G was enabled prior to
the software interrupt the RETI instruction must be used to return from interrupt in order to restore G to one. However, if G
was not enabled prior to the software interrupt the RET instruction must be used.
In the case of simultaneous multiple interrupts, the microcontroller core prioritizes the interrupts. See
Table 23
for the interrupt
service priority sequence.
Figure 18. Basic Interrupt Structure
G
INTR
PWM T1
T0
MIW
Interrupt
Pending
Flags
Interrupt Enable Bits
Global Interrupt
Enable
Interrupt
I
ADC
T1EN
T0INT
EN
WKINT
EN
AINT
EN
T1PND
T0PND
WKPND
APND
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