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參數資料
| 型號： | FPD87392BXBVQ |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | +3.3V TFT-LCD Timing Controller with Dual LVDS Inputs/Dual RSDS⑩ Outputs for TFT-LCD Monitor and Notebook (SXGA/SXGA+/UXGA) |
| 中文描述： | 3.3 TFT - LCD的雙LVDS輸入定時控制器/雙⑩輸出區特別職務隊的TFT - LCD顯示器和筆記本電腦（SXGA / SXGA / UXGA）下 |
| 文件頁數： | 28/30頁 |
| 文件大小： | 1980K |
| 代理商： | FPD87392BXBVQ |
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Appendix 1. DE Mode Timing Details
DE Mode (Disabled SYNC Pin)
Always true whenever DE is exist as inputted signal. If V
, H
and DE are available, DE mode is superior and generate
the control timing. “V-blank Detection” period is two cycles of the previous DE signals. After the V-blank detection period,
“Counter” start to count whenever DE signal available followed on the rising edge.
Case 1: Disabled Failure Detection Mode
20104323
Case 2: Enabled Failure Detection Mode (SXGA). Please refer to the “Failure Detect” on page 10.
Appendix 2. Free Run Mode Function (B/O Pin FRM “Low” to Disable)
Either input DE signal, ENA, on the DE mode or V
SYNC
on the SYNC mode are lost more than 5 frames (here, “lost” means ENA
or V
SYNC
signal more than 5 frames without change), then the TCON will enter the Free Run Mode. In the Free Run Mode, the
vertical and horizontal period will follow VESA 60 Hz standard and output data will be in the Low Level.
When TCON detects input signal back to normal (“normal” means ENA or V
signal has to change from Low Level to High
Level), then output control signals will return to the Normal Mode. In the next frame, output data will also return to Normal Mode.
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