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參數資料
| 型號： | FR65E |
| 廠商： | Fujitsu Limited |
| 英文描述： | 32-Bit Microcontroller |
| 中文描述： | 32位微控制器 |
| 文件頁數： | 63/87頁 |
| 文件大小： | 369K |
| 代理商： | FR65E |
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MB91307B
63
10. External Interface
(1) Overview
The external interface controller controls the interface between the LSI’s internal bus and external memory or I/
O devices.
This section describes the functions of the external interface.
(2) Features
Up to 32 bit-length (4 Gbyte space) address output.
Connects directly to many external memory (8 bit/16 bit) devices, allows control of multiple access timings.
Asynchronous SRAM, asynchronous ROM/Flash memory (multiple write strobe type or byte enable type)
Page mode ROM/flash memory (2/4/8 page size enabled)
Burst ROM/Flash memory (MBM29BL160D/161D/162D etc.)
Address/data multiplexed bus (8 bit/16 bit width only)
Synchronous memory* (ASIC built-in memory etc.)
*: Does not connect to synchronous SRAM.
8 independent bank (chip select area) settings, each with corresponding ship select output available
Each area size can be set in multiples of 64 KB (from 64 KB to 2 GB per chip select area).
Each area can be set in any desired area of logic address space (boundaries limited by area size).
The following functions can be independently set for each chip select area.
Chip select area enable/disable (no access to prohibited areas)
Access timing type for each area, etc.
Detailed access timing settings (individual access type settings for wait cycle, etc.)
Data bus width setting (8 bit/16 bit)
Byte ordering endian setting* (big or little).
*: CS0 area available with big endian only.
Write prohibited setting (read-only areas)
Internal cache loading enable/disable settings
Pre-fetch function enable/disable settings
Maximum burst length setting (1,2,4,8)
Different detailed timing settings for each access timing type
Different settings can be used for each chip select area even for the same access timing type.
Auto wait setting up to 15 cycles (asynchronous SRAM, ROM, Flash, I/O areas)
Bus cycle extension with external RDY input enabled (asynchronous SRAM, ROM, Flash, I/O areas)
First access wait and page wait settings enabled (burst, page mode ROM/FLASH areas)
Different idle, recovery cycles setup delay insertion etc. enabled
Fly-by transfer with DMA enabled
Transfer between memory and I/O with 1 access
Memory wait cycle can be synchronized with I/O wait cycle during fly-by
Hold time can be obtained by delaying transfer access only
Specific idle/recovery cycles can be set for fly-by transfer
External bus arbitration using BRQ and BGRNT enabled
Pins not used in external interface can be set for use as general purpose I/O ports
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