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參數資料
| 型號： | FS8160 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 1.1 GHz/1.1 GHz Dual Phase-locked Loop IC |
| 中文描述： | 1.1 GHz/1.1 GHz雙鎖相環集成電路 |
| 文件頁數： | 6/13頁 |
| 文件大?。?/td> | 257K |
| 代理商： | FS8160 |
FS8160
Page 6
April 2003
Functional Description
The FS8160 dual phase-locked loop (PLL) IC contains two identical PLLs (main and aux-
iliary). Both the main and auxiliary PLLs share the crystal oscillator, serial data input
logic, and multi-function lock detector output circuits. Each PLL has its own program-
mable input and reference frequency dividers, phase/frequency detectors, programmable
charge pumps, and digital-filtered lock detectors.
Programmable Input Frequency Divider
The VCO input to the FIN pin is divided by the programmable divider and then internally
output to the phase/frequency detector (PFD) as
f
V
. The programmable input frequency
divider consists of a ÷ 16/17 (
P
/
P
+1) dual-modulus prescaler and a 16-bit (
N
) counter,
which is further comprised of a 4-bit swallow (
A
) counter, and a 12-bit main (
B
) counter.
The total divide ratio,
M
, is related to values for
P
,
A
, and
B
through the relation
with
P
The minimum programmable divisor for continuous counting is given by
and the valid total divide ratio range for the input
16
15
×
240,
=
=
240 to 65535.
=
divider is
Programmable Reference Frequency Divider
The crystal oscillator output is divided by the programmable divider and then internally
output to the PFD as
f
R
. The programmable reference frequency divider consists of a 13-
bit reference (
R
) counter. Because of its design, the valid total divide ratio range for the
reference divider is
R
2 to 4095.
=
M
P
1
+
(
)
A
P
B
(
A
–
)
×
+
×
P
B
A,
+
×
=
=
B
P
(
A.
1
–
M
≥
)
×
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