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參數資料
| 型號： | FS8160 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 1.1 GHz/1.1 GHz Dual Phase-locked Loop IC |
| 中文描述： | 1.1 GHz/1.1 GHz雙鎖相環集成電路 |
| 文件頁數： | 9/13頁 |
| 文件大小： | 257K |
| 代理商： | FS8160 |
FS8160
Page 9
April 2003
Similarly, the 16-bit main and auxiliary input (
N
) divider ratios are specified by the
MAINA[3:0] + MAINB[11:0] and AUXA[3:0] + AUXB[11:0] bits, respectively, and are
defined in the table below.
The charge pump control bits CP_CNTRL[3:0] set (1) the phase detector polarity and (2)
the magnitude of the charge pump source/sink current, and are defined below.
Table 4: Input divider ratios
Divide
Ratio
MAINB[11:0] and AUXB[11:0]
Divide
Ratio
MAINA[3:0] and
AUXA[3:0]
11
10
9
8
7
6
5
4
3
2
1
0
3
2
1
0
3
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
4
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
4095
1
1
1
1
1
1
1
1
1
1
1
1
15
1
1
1
1
Table 5: Charge pump and PFD control bits
Bit
Latch Location
Function
“0”
“1”
CP_CNTRL[3]
Main R, bit 17
Aux. charge pump current
Low, 160
μ
A
High, 1600
μ
A
CP_CNTRL[2]
Main R, bit 16
Main charge pump current
Low, 160
μ
A
High, 1600
μ
A
CP_CNTRL[1]
Main R, bit 15
Aux. phase/frequency detector polarity
a
a. When the VCO frequency
increases
with increasing control voltage, set the phase/frequency detector
polarity to
positive
. When the VCO frequency
decreases
with increasing control voltage, set the
phase/frequency detector polarity to
negative
.
Negative
Positive
CP_CNTRL[0]
Main R, bit 14
Main phase/frequency detector polarity
Negative
Positive
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