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參數(shù)資料
| 型號： | FSLBOT |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 2/46頁 |
| 文件大小： | 0K |
| 描述： | KIT TOWER MECH BOARD |
| 視頻文件： | Freescale Tower Overview - Another Geek Moment Freescale Tower Labs 1 & 2 - Another Geek Moment |
| 特色產(chǎn)品： | Tower Mechatronics Board and Robot |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | ColdFire® |
| 主要目的： | 機器人 |
| 嵌入式： | 否 |
| 主要屬性： | 步行機器人結(jié)構(gòu) |
| 已供物品： | 線路板，4 PWM 伺服系統(tǒng)，用戶指南，匯編指令 |
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Family Configurations
MCF52259 ColdFire Microcontroller, Rev. 5
Freescale
10
1.2.5
On-Chip Memories
1.2.5.1
SRAM
The dual-ported SRAM module provides a general-purpose 64 KB memory block that the ColdFire core can access in a single
cycle. The location of the memory block can be set to any 64 KB boundary within the 4 GB address space. This memory is ideal
for storing critical code or data structures and for use as the system stack. Because the SRAM module is physically connected
to the processor's high-speed local bus, it can quickly service core-initiated accesses or memory-referencing commands from
the debug module.
The SRAM module is also accessible by the DMA, FEC, and USB. The dual-ported nature of the SRAM makes it ideal for
implementing applications with double-buffer schemes, where the processor and a DMA device operate in alternate regions of
the SRAM to maximize system performance.
1.2.5.2
Flash Memory
The ColdFire flash module (CFM) is a non-volatile memory (NVM) module that connects to the processor’s high-speed local
bus. The CFM is constructed with four banks of 64 KB
16-bit flash memory arrays to generate 512 KB of 32-bit flash memory.
These electrically erasable and programmable arrays serve as non-volatile program and data memory. The flash memory is ideal
for program and data storage for single-chip applications, allowing for field reprogramming without requiring an external high
voltage source. The CFM interfaces to the ColdFire core through an optimized read-only memory controller that supports
interleaved accesses from the 2-cycle flash memory arrays. A backdoor mapping of the flash memory is used for all program,
erase, and verify operations, as well as providing a read datapath for the DMA. Flash memory may also be programmed via the
EzPort, which is a serial flash memory programming interface that allows the flash memory to be read, erased and programmed
by an external controller in a format compatible with most SPI bus flash memory chips.
1.2.6
Cryptographic Acceleration Unit
The MCF52235 device incorporates two hardware accelerators for cryptographic functions. First, the CAU is a coprocessor
tightly-coupled to the V2 ColdFire core that implements a set of specialized operations to increase the throughput of
software-based encryption and message digest functions, specifically the DES, 3DES, AES, MD5 and SHA-1 algorithms.
Second, a random number generator provides FIPS-140 compliant 32-bit values to security processing routines. Both modules
supply critical acceleration to software-based cryptographic algorithms at a minimal hardware cost.
1.2.7
Power Management
The device incorporates several low-power modes of operation entered under program control and exited by several external
trigger events. An integrated power-on reset (POR) circuit monitors the input supply and forces an MCU reset as the supply
voltage rises. The low voltage detector (LVD) monitors the supply voltage and is configurable to force a reset or interrupt
condition if it falls below the LVD trip point. The RAM standby switch provides power to RAM when the supply voltage to the
chip falls below the standby battery voltage.
1.2.8
FlexCAN
The FlexCAN module is a communication controller implementing version 2.0 of the CAN protocol parts A and B. The CAN
protocol can be used as an industrial control serial data bus, meeting the specific requirements of reliable operation in a harsh
EMI environment with high bandwidth. This instantiation of FlexCAN has 16 message buffers.
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