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參數資料
| 型號： | FSLBOT |
| 廠商： | Freescale Semiconductor |
| 文件頁數： | 45/46頁 |
| 文件大小： | 0K |
| 描述： | KIT TOWER MECH BOARD |
| 視頻文件： | Freescale Tower Overview - Another Geek Moment Freescale Tower Labs 1 & 2 - Another Geek Moment |
| 特色產品： | Tower Mechatronics Board and Robot |
| 標準包裝： | 1 |
| 系列： | ColdFire® |
| 主要目的： | 機器人 |
| 嵌入式： | 否 |
| 主要屬性： | 步行機器人結構 |
| 已供物品： | 線路板，4 PWM 伺服系統，用戶指南，匯編指令 |
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Family Configurations
MCF52259 ColdFire Microcontroller, Rev. 5
Freescale
8
— Pre-divider capable of dividing the clock source frequency into the PLL reference frequency range
— System can be clocked from PLL or directly from crystal oscillator or relaxation oscillator
— Low power modes supported
—2n (0
n 15) low-power divider for extremely low frequency operation
Interrupt controller
— Uniquely programmable vectors for all interrupt sources
— Fully programmable level and priority for all peripheral interrupt sources
— Seven external interrupt signals with fixed level and priority
— Unique vector number for each interrupt source
— Ability to mask any individual interrupt source or all interrupt sources (global mask-all)
— Support for hardware and software interrupt acknowledge (IACK) cycles
— Combinatorial path to provide wake-up from low-power modes
DMA controller
— Four fully programmable channels
— Dual-address transfer support with 8-, 16-, and 32-bit data capability, along with support for 16-byte (4
32-bit)
burst transfers
— Source/destination address pointers that can increment or remain constant
— 24-bit byte transfer counter per channel
— Auto-alignment transfers supported for efficient block movement
— Bursting and cycle-steal support
— Software-programmable DMA requests for the UARTs (3) and 32-bit timers (4)
— Channel linking support
Reset
— Separate reset in and reset out signals
— Seven sources of reset:
– Power-on reset (POR)
– External
–Software
– Watchdog
– Loss of clock / loss of lock
– Low-voltage detection (LVD)
–JTAG
— Status flag indication of source of last reset
Chip configuration module (CCM)
— System configuration during reset
— Selects one of six clock modes
— Configures output pad drive strength
— Unique part identification number and part revision number
General purpose I/O interface
— Up to 56 bits of general purpose I/O on 100-pin package
— Up to 96 bits of general purpose I/O on 144-pin package
— Bit manipulation supported via set/clear functions
— Programmable drive strengths
— Unused peripheral pins may be used as extra GPIO
JTAG support for system level board testing
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