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參數(shù)資料
型號: GS1532-CFE3
廠商: Gennum Corporation
英文描述: GS1532 HD-LINX-TM II Multi-Rate Serializer
中文描述: GS1532的HD - LINX進(jìn)程,商標(biāo)第二多速率串行器
文件頁數(shù): 13/52頁
文件大小: 512K
代理商: GS1532-CFE3
GS1532 Data Sheet
21498 - 6
June 2005
13 of 52
69
PCLK
Input
PARALLEL DATA BUS CLOCK
Signal levels are LVCMOS/LVTTL compatible.
HD 20-bit mode
PCLK = 74.25MHz or 74.25/1.001MHz
HD 10-bit mode
PCLK = 148.5MHz or 148.5/1.001MHz
SD 20-bit mode
PCLK = 13.5MHz
SD 10-bit mode
PCLK = 27MHz
72
LOCKED
Synchronous
with PCLK
Output
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS / LVTTL compatible.
The LOCKED signal will be HIGH whenever the device has correctly
received and locked to SMPTE compliant data in SMPTE mode or
DVB-ASI compliant data in DVB-ASI mode, or when the device has
achieved lock in Data-Through mode.
It will be LOW otherwise.
73, 74
VCO, VCO
Analog
Input
Differential inputs for the external VCO reference signal. For single ended
devices such as the GO1525, VCO should be AC coupled to VCO_GND.
VCO is nominally 1.485GHz.
75
VCO_GND
Output
Power
Ground reference for the external voltage controlled oscillator. Connect to
pins 2, 4, 6, and 8 of the GO1525. This pin is an output.
Should be isolated from all other grounds.
76
VCO_VCC
Output
Power
Power supply for the external voltage controlled oscillator. Connect to pin
7 of the GO1525. This pin is an output.
Should be isolated from all other power supplies.
77
LF
Analog
Output
Control voltage to external voltage controlled oscillator. Nominally +1.25V
DC.
78
CP_CAP
Analog
Input
PLL lock time constant capacitor connection. Normally connected to
VCO_GND through 2.2nF.
79
LB_CONT
Analog
Input
Control voltage to set the loop bandwidth of the integrated reclocker.
Normally connected to VCO_VDD through 15k
Ω
.
80
CP_GND
Power
Ground connection for the charge pump. Connect to analog GND.
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description
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