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參數資料
| 型號： | GS1559-CB |
| 廠商： | Gennum Corporation |
| 英文描述： | GS1559 HD-LINX-TM II Multi-Rate Deserializer with Loop-Through Cable Driver |
| 中文描述： | GS1559的HD - LINX進程，商標第二多速率解串器與環通電纜驅動器 |
| 文件頁數： | 31/74頁 |
| 文件大小： | 686K |
| 代理商： | GS1559-CB |
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GS1559 Data Sheet
30572 - 4
July 2005
31 of 74
4.6 Modes Of Operation
The GS1559 has two basic modes of operation which determine how the lock
detect block controls the integrated reclocker. Master mode is enabled when the
application layer sets the MASTER/SLAVE pin HIGH, and slave mode is enabled
when MASTER/SLAVE is set LOW.
4.6.1 Lock Detect
The lock detect block controls the center frequency of the integrated reclocker to
ensure lock to the received serial digital data stream is achieved, and indicates via
the LOCKED output pin that the device has detected the appropriate sync words.
In Data through mode the detection for appropriate sync words is turned off. The
locked pin is an indication of analog lock.
Lock detection is a continuous process, which begins at device power up or after
a system reset, and continues until the device is powered down or held in reset.
The lock detection algorithm first determines if a valid serial digital input signal has
been presented to the device by sampling the internal carrier_detect signal. As
described in
Carrier Detect Input on page 27
, this signal will be LOW when a good
serial digital input signal has been detected.
If the carrier_detect signal is HIGH, the serial data into the device is considered
invalid, and the VCO frequency will be set to the center of the pull range. The
LOCKED pin will be LOW and all outputs of the device except for the PCLK output
will be muted. Instead, the PCLK output frequency will operate within +/-3% of the
rates shown in
Table 4-16
of
Parallel Output Clock (PCLK) on page 63
.
NOTE: When the device is operating in DVB-ASI slave mode only, the parallel
outputs will not mute when the carrier_detect signal is HIGH. The LOCKED signal
will function normally.
If a valid input signal has been detected, and the device is in master mode, the lock
algorithm will enter a hunt phase where four attempts are made to detect the
presence of either SMPTE TRS sync words or DVB-ASI sync words. At each
attempt, the center frequency of the reclocker will be toggled between 270Mb/s and
1.485Gb/s.
Assuming that a valid SMPTE or DVB-ASI signal has been applied to the device,
asynchronous lock times will be as listed in
Table 2-2
.
In slave mode, the application layer fixes the center frequency of the reclocker such
that the lock algorithm will attempt to lock within the single data rate determined by
the setting of the SD/HD pin. Asynchronous lock times are also listed in the
Table 2-2
.
NOTE: The PCLK output will continue to operate during the lock detection process.
The frequency may toggle between 148MHz and 27MHz when the 20bit/10bit pin
is set LOW, or between 74MHz and 13.5MHz when 20bit/10bit is set HIGH.
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相關代理商/技術參數 |
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| GS1559CBE2 | 制造商:Gennum Corporation 功能描述:DESERIALISER HD/SDI/ASI W/DRV 100BGA 制造商:Gennum Corporation 功能描述:DESERIALISER, HD/SDI/ASI, W/DRV, 100BGA |
| GS1559-CBE2 | 功能描述:RF, RFID, WIRELESS RoHS:是 類別:集成電路 (IC) >> 接口 - 串行器，解串行器 系列:* 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 功能:解串器 數據速率:2.5Gbps 輸入類型:串行 輸出類型:并聯 輸入數:- 輸出數:24 電源電壓:1.8 V ~ 3.3 V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:64-TQFP 裸露焊盤 供應商設備封裝:64-TQFP-EP（10x10） 包裝:管件 |
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| GS1560A | 制造商:Gennum Corporation 功能描述: |
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