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參數資料
| 型號： | GS816218BGD-250 |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | 1M x 18, 512K x 36 18MbS/DCD Sync Burst SRAMs |
| 中文描述： | 1M X 18 CACHE SRAM, 5.5 ns, PBGA165 |
| 封裝： | ROHS COMPLIANT, FBGA-165 |
| 文件頁數： | 25/37頁 |
| 文件大小： | 866K |
| 代理商： | GS816218BGD-250 |
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GS816218/36B(B/D)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04 9/2005
25/37
2004, GSI Technology
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
Instruction Register
ID Code Register
·
31 30 29
Boundary Scan Register
0
1
2
0
· · ·
1
2
0
Bypass Register
TDI
TDO
TMS
TCK
Test Access Port (TAP) Controller
1
·
1
0
·
·
·
·
·
·
·
·
·
Control Signals
·
JTAG TAP Block Diagram
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
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相關代理商/技術參數 |
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| GS816218BGD-250V | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 18MBIT 1MX18 5.5NS/2.5NS 165FPBGA - Trays |
| GS816218DB-150 | 制造商:GSI Technology 功能描述:119 BGA - Bulk |
| GS816218DB-150I | 制造商:GSI Technology 功能描述:119 BGA - Bulk |
| GS816218DB-150IV | 制造商:GSI Technology 功能描述:119 BGA - Bulk |
| GS816218DB-150V | 制造商:GSI Technology 功能描述:119 BGA - Bulk |
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