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參數資料
| 型號： | GS816218BGD-250 |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | 1M x 18, 512K x 36 18MbS/DCD Sync Burst SRAMs |
| 中文描述： | 1M X 18 CACHE SRAM, 5.5 ns, PBGA165 |
| 封裝： | ROHS COMPLIANT, FBGA-165 |
| 文件頁數： | 8/37頁 |
| 文件大小： | 866K |
| 代理商： | GS816218BGD-250 |
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Mode Pin Functions
Mode Name
Pin
Name
State
Function
Burst Order Control
LBO
L
H
Linear Burst
Interleaved Burst
Active
Standby, I
DD
= I
SB
Dual Cycle Deselect
Single Cycle Deselect
High Drive (Low Impedance)
Low Drive (High Impedance)
Power Down Control
ZZ
L or NC
H
Single/Dual Cycle Deselect Control
SCD
L
H or NC
L
H or NC
FLXDrive Output Impedance Control
ZQ
GS816218/36B(B/D)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04 9/2005
8/37
2004, GSI Technology
Note:
There are pull-up devices on the ZQ,SCD, and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the
chip will operate in the default states as specified in the above tables.
Note:
The burst counter wraps to initial state on the 5th clock.
Note:
The burst counter wraps to initial state on the 5th clock.
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00
Burst Counter Sequences
BPR 1999.05.18
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相關代理商/技術參數 |
參數描述 |
|---|---|
| GS816218BGD-250V | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 18MBIT 1MX18 5.5NS/2.5NS 165FPBGA - Trays |
| GS816218DB-150 | 制造商:GSI Technology 功能描述:119 BGA - Bulk |
| GS816218DB-150I | 制造商:GSI Technology 功能描述:119 BGA - Bulk |
| GS816218DB-150IV | 制造商:GSI Technology 功能描述:119 BGA - Bulk |
| GS816218DB-150V | 制造商:GSI Technology 功能描述:119 BGA - Bulk |
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