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參數資料
| 型號： | GS816272CGC-333 |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | 256K x 72 18Mb S/DCD Sync Burst SRAMs |
| 中文描述： | 256K X 72 CACHE SRAM, 4.5 ns, PBGA209 |
| 封裝： | 14 X 22 MM, 1 MM PITCH, ROHS COMPLIANT, BGA-209 |
| 文件頁數： | 1/31頁 |
| 文件大小： | 678K |
| 代理商： | GS816272CGC-333 |
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GS816272CC-333/300/250/200/150
256K x 72
18Mb S/DCD Sync Burst SRAMs
333 MHz
–
150 MHz
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
209-Bump BGA
Commercial Temp
Industrial Temp
Preliminary
Rev: 1.01 2/2005
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
1/31
2004, GSI Technology
Features
FT pin for user-configurable flow through or pipeline operation
Single/Dual Cycle Deselect selectable
IEEE 1149.1 JTAG-compatible Boundary Scan
ZQ mode pin for user-selectable high/low output drive
2.5 V or 3.3 V +10%/–10% core power supply
LBO pin for Linear or Interleaved Burst mode
Internal input resistors on mode pins allow floating mode pins
Default to SCD x18/x36 Interleaved Pipeline mode
Byte Write (BW) and/or Global Write (GW) operation
Internal self-timed write cycle
Automatic power-down for portable applications
JEDEC-standard 209-bump BGA package
Pb-Free 209-bump BGA package available
Functional Description
Applications
The GS816272CC is an 18,874,368-bit high performance
synchronous SRAM with a 2-bit burst address counter. Although of a
type originally developed for Level 2 Cache applications supporting
high performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main store to
networking chip set support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control inputs
(ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are
synchronous and are controlled by a positive-edge-triggered clock
input (CK). Output enable (G) and power down control (ZZ) are
asynchronous inputs. Burst cycles can be initiated with either ADSP
or ADSC inputs. In Burst mode, subsequent burst addresses are
generated internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or interleave order
with the Linear Burst Order (LBO) input. The Burst function need not
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the user
via the FT mode . Holding the FT mode pin low places the RAM in
Flow Through mode, causing output data to bypass the Data Output
Register. Holding FT high places the RAM in Pipeline mode,
activating the rising-edge-triggered Data Output Register.
SCD and DCD Pipelined Reads
The GS816272CC is an SCD (Single Cycle Deselect) and DCD (Dual
Cycle Deselect) pipelined synchronous SRAM. DCD SRAMs
pipeline disable commands to the same degree as read commands.
SCD SRAMs pipeline deselect commands one stage less than read
commands. SCD RAMs begin turning off their outputs immediately
after the deselect command has been captured in the input registers.
DCD RAMs hold the deselect command for one full cycle and then
begin turning off their outputs just after the second rising edge of
clock. The user may configure this SRAM for either mode of
operation using the SCD mode input.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable (BW)
input combined with one or more individual byte write signals (Bx).
In addition, Global Write (GW) is available for writing all bytes at one
time, regardless of the Byte Write control inputs.
FLXDrive
The ZQ pin allows selection between high drive strength (ZQ low) for
multi-drop bus applications and normal drive strength (ZQ floating or
high) point-to-point applications. See the Output Driver
Characteristics chart for details.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of
the ZZ signal, or by stopping the clock (CK). Memory data is retained
during Sleep mode.
Core and Interface Voltages
The GS816272CC operates on a 2.5 V or 3.3 V power supply. All
input are 3.3 V and 2.5 V compatible. Separate output power (V
DDQ
)
pins are used to decouple output noise from the internal circuits and
are 3.3 V and 2.5 V compatible.
Parameter Synopsis
-333
-300
-250
-200
-150
Unit
Pipeline
3-1-1-1
t
KQ
tCycle
Curr
t
KQ
tCycle
Curr
2.8
3.0
2.8
3.3
3.0
4.0
3.0
5.0
3.8
6.7
ns
ns
545
4.5
4.5
380
495
5.0
5.0
345
425
5.5
5.5
315
345
6.5
6.5
275
270
7.5
7.5
250
mA
ns
ns
mA
Flow Through
2-1-1-1
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相關代理商/技術參數 |
參數描述 |
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| GS816273C-133 | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 2.5V/3.3V 18MBIT 256KX72 3.5NS 209FBGA - Trays |
| GS816273C-133I | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 2.5V/3.3V 18MBIT 256KX72 3.5NS 209FBGA - Trays |
| GS816273C-150 | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 2.5V/3.3V 18MBIT 256KX72 3.3NS 209FBGA - Trays |
| GS816273C-150I | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 2.5V/3.3V 18MBIT 256KX72 3.3NS 209FBGA - Trays |
| GS816273C-166 | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 2.5V/3.3V 18MBIT 256KX72 2.9NS 209FBGA - Trays |
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