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參數(shù)資料
| 型號： | GS8170LW72C-333 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Low-Noise Operational Amplifier 8-PDIP -40 to 85 |
| 中文描述： | 35.7西格馬1x1Lp的CMOS的I / O后寫入SigmaRAM |
| 文件頁數(shù)： | 22/27頁 |
| 文件大小： | 884K |
| 代理商： | GS8170LW72C-333 |
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GS8170LW36/72C-333/300/250/200
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 2.03 1/2005
22/27
2002, GSI Technology, Inc.
JTAG Port AC Test Conditions
JTAG TAP Instruction Set Summary
Instruction
Code
Description
Notes
EXTEST
000
Places the Boundary Scan Register between TDI and TDO.
1
IDCODE
001
Preloads ID Register and places it between TDI and TDO.
1, 2
SAMPLE-Z
010
Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
Forces all RAM output drivers to High-Z.
1
RFU
011
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
1
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
1
GSI
101
GSI private instruction.
1
RFU
110
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
1
BYPASS
111
Places Bypass Register between TDI and TDO.
1
Notes:
1.
2.
Instruction codes expressed in binary, MSB on left, LSB on right.
Default instruction automatically loaded at power-up and in test-logic-reset state.
Notes:
1.
2.
Include scope and jig capacitance.
Test conditions as as shown unless otherwise noted.
Parameter
Conditions
Input high level
V
DD
– 0.2 V
Input low level
0.2 V
Input slew rate
1 V/ns
Input reference level
V
DDQ
/2
Output reference level
V
DDQ
/2
DQ
V
DDQ
/2
50
30pF
*
JTAG Port AC Test Load
* Distributed Test Jig Capacitance
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