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參數資料
| 型號： | GS8170LW72C-333I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 18Mb sigma 1x1Lp CMOS I/O Late Write SigmaRAM |
| 中文描述： | 35.7西格馬1x1Lp的CMOS的I / O后寫入SigmaRAM |
| 文件頁數： | 19/27頁 |
| 文件大小： | 884K |
| 代理商： | GS8170LW72C-333I |
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GS8170LW36/72C-333/300/250/200
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 2.03 1/2005
19/27
2002, GSI Technology, Inc.
JTAG TAP Block Diagram
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with
the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the
RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the
register is the LSB and the first to reach TDO when shifting begins.
ID Register Contents
Die
Revision
Code
Not Used
I/O
Configuration
GSI Technology
JEDEC Vendor
ID Code
P
Bit #
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
x72
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0 1 1 0 1 1 0 0 1
1
x36
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0 1 1 0 1 1 0 0 1
1
Instruction Register
ID Code Register
·
31 30 29
Boundary Scan Register
0
1
2
0
· · ·
1
2
0
Bypass Register
TDI
TDO
TMS
TCK
Test Access Port (TAP) Controller
1
·
1
0
·
·
·
·
·
·
·
·
·
Control Signals
·
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PDF描述 |
|---|---|
| GS8170LW36C-333I | 18Mb sigma 1x1Lp CMOS I/O Late Write SigmaRAM |
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| GS8170LW36C-200 | Low-Noise Operational Amplifier 8-PDIP -40 to 85 |
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| GS8170LW36C-250 | Low-Noise Operational Amplifier 8-SO -40 to 85 |
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