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參數(shù)資料
型號(hào): GS8322V72GC-250I
廠商: GSI TECHNOLOGY
元件分類(lèi): DRAM
英文描述: 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs
中文描述: 512K X 72 CACHE SRAM, 6.5 ns, PBGA209
封裝: 14 X 22 MM, 1 MM PITCH, LEAD FREE, BGA-209
文件頁(yè)數(shù): 21/42頁(yè)
文件大小: 1038K
代理商: GS8322V72GC-250I
AC Electrical Characteristics
Parameter
Symbol
-250
-225
-200
-166
-150
-133
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Pipeline
Clock Cycle Time
tKC
4.0
4.4
5.0
6.0
6.7
7.5
ns
Clock to Output Valid (x18/x36)
tKQ
2.5
2.7
3.0
3.5
3.8
4.0
ns
Clock to Output Valid (x72)
tKQ
3.0
3.0
3.0
3.5
3.8
4.0
ns
Clock to Output Invalid
tKQX
1.5
1.5
1.5
1.5
1.5
1.5
ns
Clock to Output in Low-Z
tLZ
1
1.5
1.5
1.5
1.5
1.5
1.5
ns
Setup time
tS
1.2
1.3
1.4
1.5
1.5
1.5
ns
Hold time
tH
0.2
0.3
0.4
0.5
0.5
0.5
ns
Flow
Through
Clock Cycle Time
tKC
6.5
7.0
7.5
8.0
8.5
8.5
ns
Clock to Output Valid
tKQ
6.5
7.0
7.5
8.0
8.5
8.5
ns
Clock to Output Invalid
tKQX
3.0
3.0
3.0
3.0
3.0
3.0
ns
Clock to Output in Low-Z
tLZ
1
3.0
3.0
3.0
3.0
3.0
3.0
ns
Setup time
tS
1.5
1.5
1.5
1.5
1.5
1.5
ns
Hold time
tH
0.5
0.5
0.5
0.5
0.5
0.5
ns
Clock HIGH Time
tKH
1.3
1.3
1.3
1.3
1.5
1.7
ns
Clock LOW Time
tKL
1.5
1.5
1.5
1.5
1.7
2
ns
Clock to Output in
High-Z (x18/x36)
tHZ
1
1.5
2.5
1.5
2.7
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
ns
Clock to Output in
High-Z (x72)
tHZ
1
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
ns
G to Output Valid
(x18/x36)
tOE
2.5
2.7
3.0
3.5
3.8
4.0
ns
G to Output Valid
(x72)
tOE
3.0
3.0
3.0
3.5
3.8
4.0
ns
G to output in Low-Z
tOLZ
1
0
0
0
0
0
0
ns
G to output in High-Z (x18/x36)
tOHZ
1
2.5
2.7
3.0
3.0
3.0
3.0
ns
G to output in High-Z (x72)
tOHZ
1
3.0
3.0
3.0
3.0
3.0
3.0
ns
ZZ setup time
tZZS
2
5
5
5
5
5
5
ns
ZZ hold time
tZZH
2
1
1
1
1
1
1
ns
ZZ recovery
tZZR
20
20
20
20
20
20
ns
Preliminary
GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04 4/2005
21/42
2003, GSI Technology
Notes:
1.
2.
These parameters are sampled and are not 100% tested.
ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
相關(guān)PDF資料
PDF描述
GS8322V18GE-225 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs
GS8322V18GE-225I 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs
GS8322V18GE-250 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs
GS8322V18GE-250I 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs
GS8322V36B-133 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs
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