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參數(shù)資料
| 型號(hào)： | GS8322ZV18B-250 |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | 36Mb Pipelined and Flow Through Synchronous NBT SRAM |
| 中文描述： | 2M X 18 ZBT SRAM, 6.5 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 1.27 PITCH, FPBGA-119 |
| 文件頁數(shù)： | 19/39頁 |
| 文件大小： | 975K |
| 代理商： | GS8322ZV18B-250 |
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GS8322ZV18(B/E)/GS8322ZV36(B/E)/GS8322ZV72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03a 2/2006
19/39
2002, GSI Technology
Logic Levels
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
V
DD
Input High Voltage
V
IH
0.6*V
DD
—
V
DD
+ 0.3
V
1
V
DD
Input Low Voltage
V
IL
–
0.3
—
0.3*V
DD
V
1
V
DDQ
I/O Input High Voltage
V
IHQ
0.6*V
DD
—
V
DDQ
+ 0.3
V
1,3
V
DDQ
I/O Input Low Voltage
V
ILQ
–
0.3
—
0.3*V
DD
V
1,3
Notes:
1.
The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
Input Under/overshoot voltage must be
–
2 V > Vi < V
DDn
+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tKC.
V
IHQ
(max) is voltage on V
DDQ
pins plus 0.3 V.
2.
3.
20% tKC
V
SS
–
2.0 V
50%
V
SS
V
IH
Undershoot Measurement and Timing
Overshoot Measurement and Timing
20% tKC
V
DD
+ 2.0 V
50%
V
DD
V
IL
Capacitance
(T
A
= 25
o
C, f = 1 MH
Z
, V
DD
Parameter
Symbol
Test conditions
Typ.
Max.
Unit
Input Capacitance
C
IN
V
IN
= 0 V
4
5
pF
Input/Output Capacitance
C
I/O
V
OUT
= 0 V
6
7
pF
Note:
These parameters are sample tested.
= 2.5 V)
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| GS8322ZV72C-133 | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V 36MBIT 512KX72 8.5NS/4NS 209FBGA - Trays |
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| GS8324Z36B-200I | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 2.5V/3.3V 36MBIT 1MX36 7.5NS/3NS 119FBGA - Trays |
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