- 您現在的位置：買賣IC網 > PDF目錄385330 > GS8642ZV18B (GSI TECHNOLOGY) 72Mb Pipelined and Flow Through Synchronous NBT SRAM PDF資料下載
參數資料
| 型號： | GS8642ZV18B |
| 廠商： | GSI TECHNOLOGY |
| 英文描述： | 72Mb Pipelined and Flow Through Synchronous NBT SRAM |
| 中文描述： | 72Mb流水線和流量，通過同步唑的SRAM |
| 文件頁數： | 13/32頁 |
| 文件大小： | 805K |
| 代理商： | GS8642ZV18B |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁當前第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁
Product Preview
GS8642ZV18(B)/GS8642ZV36(B)/GS8642ZV72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 5/2005
13/32
2004, GSI Technology
Burst Cycles
Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from
read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address
generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when
driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write
the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into
Load mode.
Burst Order
The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been
accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is Low, a linear burst
sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables
below for details.
FLXDrive
The ZQ pin allows selection between NBT RAM nominal drive strength (ZQ low) for multi-drop bus applications and low drive
strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details.
Mode Pin Functions
Mode Name
Pin Name
State
Function
Burst Order Control
LBO
L
Linear Burst
H
Interleaved Burst
Output Register Control
FT
L
Flow Through
H or NC
Pipeline
Power Down Control
ZZ
L or NC
Active
H
Standby, I
DD
= I
SB
FLXDrive Output Impedance Control
ZQ
L
High Drive (Low Impedance)
H or NC
Low Drive (High Impedance)
Note:
Thereis a are pull-up devicesonthe ZQ and FT pins and a pull-down device on the ZZ pin, so thosethis input pins can be unconnected and
the chip will operate in the default states as specified in the above tables.
相關PDF資料 |
PDF描述 |
|---|---|
| GS8642ZV18B-167 | 72Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8642ZV18B-167I | 72Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8642ZV18B-200 | 72Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8642ZV18B-200I | 72Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8642ZV18B-250 | 72Mb Pipelined and Flow Through Synchronous NBT SRAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| GS8642ZV18B-167 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8642ZV18B-167I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8642ZV18B-200 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8642ZV18B-200I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8642ZV18B-250 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb Pipelined and Flow Through Synchronous NBT SRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復。