欧美成人免费电影,国产欧美一区二区三区精品酒店,精品国产a毛片,色网在线免费观看

參數(shù)資料
型號(hào): GS8644ZV18B-200I
廠商: GSI TECHNOLOGY
元件分類: DRAM
英文描述: 72Mb Pipelined and Flow Through Synchronous NBT SRAM
中文描述: 4M X 18 ZBT SRAM, 6.5 ns, PBGA119
封裝: 14 X 22 MM, 1.27 MM PITCH, FBGA-119
文件頁數(shù): 28/37頁
文件大?。?/td> 776K
代理商: GS8644ZV18B-200I
Product Preview
GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03 11/2004
28/37
2003, GSI Technology
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with
all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is
still determined by its input pins.
Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command.
Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output
drivers on the falling edge of TCK when the controller is in the Update-IR state.
Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruc-
tion is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not asso-
ciated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR
state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associ-
ated.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and
places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction
loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-
Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR
state.
RFU
These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
相關(guān)PDF資料
PDF描述
GS8644ZV18B-225 72Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8644ZV18B-225I 72Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8644ZV18B-250 72Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8644ZV18B-250I 72Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8644ZV18E-133 72Mb Pipelined and Flow Through Synchronous NBT SRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS8644ZV18B-225 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8644ZV18B-225I 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8644ZV18B-250 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8644ZV18B-250I 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8644ZV18E-133 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb Pipelined and Flow Through Synchronous NBT SRAM
主站蜘蛛池模板: 磐石市| 瑞安市| 左云县| 河曲县| 永州市| 青田县| 界首市| 霸州市| 尉犁县| 阿坝县| 沙洋县| 长葛市| 抚顺市| 台前县| 彭阳县| 霍林郭勒市| 海兴县| 宝山区| 伊川县| 綦江县| 天柱县| 阿坝| 观塘区| 扶余县| 黄骅市| 皮山县| 怀柔区| 大连市| 屏东县| 刚察县| 华亭县| 河池市| 吉安市| 张家川| 广河县| 启东市| 霍州市| 柳江县| 仙居县| 蕲春县| 张家口市|