欧美成人免费电影,国产欧美一区二区三区精品酒店,精品国产a毛片,色网在线免费观看

參數資料
型號: GS8662D09GE-333I
廠商: GSI TECHNOLOGY
元件分類: DRAM
英文描述: 72Mb SigmaQuad-II Burst of 4 SRAM
中文描述: 8M X 9 DDR SRAM, 0.45 ns, PBGA165
封裝: 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165
文件頁數: 13/29頁
文件大小: 896K
代理商: GS8662D09GE-333I
Preliminary
GS8662D08/09/18/36E-333/300/250/200/167
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.01a 2/2006
13/29
2005, GSI Technology
FLXDrive-II Output Driver Impedance Control
HSTL I/O SigmaQuad-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to
V
SS
via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be
5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is
between 150
and 300
. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts
in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and
temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance
evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is
implemented with discrete binary weighted impedance steps. Updates of pull-down drive impedance occur whenever a driver is
producing a “1” or is High-Z. Pull-up drive impedance is updated when a driver is producing a “0” or is High-Z.
Separate I/O SigmaQuad-II B4 SRAM Truth Table
Previous
Operation
A
R
W
Current
Operation
D
D
D
D
Q
Q
Q
Q
K
(t
n-1
)
K
(t
n
)
K
(t
n
)
K
(t
n
)
K
(t
n
)
K
(t
n+1
)
K
(t
n+1
)
K
(t
n+2
)
K
(t
n+2
)
K
(t
n+1
)
K
(t
n+1
)
K
(t
n+2
)
K
(t
n+2
)
Deselect
X
1
1
Deselect
X
X
Hi-Z
Hi-Z
Write
X
1
X
Deselect
D2
D3
Hi-Z
Hi-Z
Read
X
X
1
Deselect
X
X
Q2
Q3
Deselect
V
1
0
Write
D0
D1
D2
D3
Hi-Z
Hi-Z
Deselect
V
0
X
Read
X
X
Q0
Q1
Q2
Q3
Read
V
X
0
Write
D0
D1
D2
D3
Q2
Q3
Write
V
0
X
Read
D2
D3
Q0
Q1
Q2
Q3
Notes:
1.
2.
3.
4.
5.
“1” = input “high”; “0” = input “low”; “V” = input “valid”; “X” = input “don’t care”
“—” indicates that the input requirement or output state is determined by the next operation.
Q0, Q1, Q2, and Q3 indicate the first, second, third, and fourth pieces of output data transferred during Read operations.
D0, D1, D2, and D3 indicate the first, second, third, and fourth pieces of input data transferred during Write operations.
Qs are tristated for one cycle in response to Deselect and Write commands, one cycle after the command is sampled, except when pre-
ceded by a Read command.
Users should not clock in metastable addresses.
6.
相關PDF資料
PDF描述
GS8662D18E-167 72Mb SigmaQuad-II Burst of 4 SRAM
GS8662D18E-167I 72Mb SigmaQuad-II Burst of 4 SRAM
GS8662D18E-200 72Mb SigmaQuad-II Burst of 4 SRAM
GS8662D18E-200I 72Mb SigmaQuad-II Burst of 4 SRAM
GS8662D18E-250 72Mb SigmaQuad-II Burst of 4 SRAM
相關代理商/技術參數
參數描述
GS8662D10BD-450 制造商:GSI Technology 功能描述:165 FBGA - Bulk
GS8662D11BD-350 制造商:GSI Technology 功能描述:165 FBGA - Bulk
GS8662D11BD-450 制造商:GSI Technology 功能描述:165 FBGA - Bulk
GS8662D11BD-500 制造商:GSI Technology 功能描述:165 FBGA - Bulk
GS8662D11BD-550 制造商:GSI Technology 功能描述:165 FBGA - Bulk
主站蜘蛛池模板: 时尚| 日喀则市| 文化| 康定县| 黑山县| 长宁区| 芮城县| 垦利县| 恭城| 九江县| 江源县| 南华县| 胶州市| 丘北县| 星子县| 通江县| 江源县| 子长县| 庆云县| 定西市| 济宁市| 万宁市| 鹤庆县| 正定县| 历史| 龙江县| 庆安县| 福安市| 九江市| 宜春市| 绥滨县| 陵川县| 九龙城区| 石嘴山市| 麻栗坡县| 梅州市| 平度市| 白朗县| 鸡东县| 修文县| 营口市|