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參數(shù)資料
| 型號： | GS8662Q18GE-250I |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | 72Mb SigmaQuad-II Burst of 2 SRAM |
| 中文描述： | 4M X 18 STANDARD SRAM, 0.45 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165 |
| 文件頁數(shù)： | 13/35頁 |
| 文件大小： | 993K |
| 代理商： | GS8662Q18GE-250I |
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Preliminary
GS8662Q08/09/18/36E-300/250/200/167
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.01 9/2005
13/35
2005, GSI Technology
FLXDrive-II Output Driver Impedance Control
HSTL I/O SigmaQuad-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to
V
SS
via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be
5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is
between 150
and 300
. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts
in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and
temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance
evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is
implemented with discrete binary weighted impedance steps. Updates of pull-down drive impedance occur whenever a driver is
producing a “1” or is High-Z. Pull-up drive impedance is updated when a driver is producing a “0” or is High-Z.
SigmaQuad-II B2 Coherency and Pass Through Functions
Because the SigmaQuad-II B2 read and write commands are loaded at the same time, there may be some confusion over what
constitutes “coherent” operation. Normally, one would expect a RAM to produce the just-written data when it is read immediately
after a write. This is true of the SigmaQuad-II B2 except in one case, as is illustrated in the following diagram. If the user holds the
same address value in a given K clock cycle, loading the same address as a read address and then as a matching write address, the
SigmaQuad-II B2 will read or “Pass-thru” the latest data input, rather than the data from the previously completed write operation.
Dwg Rev. G
DB0
DB1
DD0
DD1
DF0
DF1
DH0
DH1
DI0
QA0
QA1
QC0
QC1
QE0
QE1
7
1
Write
Read
OO
IO
5
6
OI
3
Write
Read
Write
C
/R
/W
/BWx
Read
Write
Address
OO
OI
OI
OO
OO
OO
Read
K
/K
D
Q
5
/C
4
6
8
2
7
1
9
H
I
A
B
C
D
E
F
G
COHERENT
PASS-THRU
SigmaQuad-II B2 Coherency and Pass Through Functions
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS8662Q18GE-300 | 72Mb SigmaQuad-II Burst of 2 SRAM |
| GS8662Q18GE-300I | 72Mb SigmaQuad-II Burst of 2 SRAM |
| GS8662Q36E-167 | 72Mb SigmaQuad-II Burst of 2 SRAM |
| GS8662Q36E-167I | 72Mb SigmaQuad-II Burst of 2 SRAM |
| GS8662Q36E-200 | 72Mb SigmaQuad-II Burst of 2 SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS8662Q18GE-300 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb SigmaQuad-II Burst of 2 SRAM |
| GS8662Q18GE-300I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb SigmaQuad-II Burst of 2 SRAM |
| GS8662Q36E-167 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb SigmaQuad-II Burst of 2 SRAM |
| GS8662Q36E-167I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb SigmaQuad-II Burst of 2 SRAM |
| GS8662Q36E-200 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb SigmaQuad-II Burst of 2 SRAM |
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