- 您現在的位置：買賣IC網 > PDF目錄385336 > GS8662R18E-250I (GSI TECHNOLOGY) 72Mb SigmaCIO DDR-II Burst of 4 SRAM PDF資料下載
參數資料
| 型號： | GS8662R18E-250I |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | 72Mb SigmaCIO DDR-II Burst of 4 SRAM |
| 中文描述： | 4M X 18 DDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 15 MM X 17 MM, 1MM PITCH, FPBGA-165 |
| 文件頁數： | 11/37頁 |
| 文件大小： | 942K |
| 代理商： | GS8662R18E-250I |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁當前第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁
Preliminary
GS8662R08/09/18/36E-333/300/250/200/167
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.01 9/2005
11/37
2005, GSI Technology
FLXDrive-II Output Driver Impedance Control
HSTL I/O SigmaCIO DDR-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected
to V
SS
via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be
5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is
between 150
and 300
. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts
in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and
temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance
evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is
implemented with discrete binary weighted impedance steps. Updates of pull-down drive impedance occur whenever a driver is
producing a “1” or is High-Z. Pull-up drive impedance is updated when a driver is producing a “0” or is High-Z.
Common I/O SigmaCIO DDR-II B4 SRAM Truth Table
K
n
LD
R/W
DQ
Operation
A + 0
A + 1
A + 2
A + 3
↑
1
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Deselect
↑
0
0
D@K
n+1
D@K
n+1
D@K
n+2
D@K
n+2
Write
↑
0
1
Q@K
n+1
or
C
n+1
Q@K
n+2
or
C
n+2
Q@K
n+2
or
C
n+2
Q@K
n+3
or
C
n+3
Read
Note:
Q is controlled by K clocks if C clocks are not used.
相關PDF資料 |
PDF描述 |
|---|---|
| GS8662R18E-300 | 72Mb SigmaCIO DDR-II Burst of 4 SRAM |
| GS8662R18E-300I | 72Mb SigmaCIO DDR-II Burst of 4 SRAM |
| GS8662R18E-333 | 72Mb SigmaCIO DDR-II Burst of 4 SRAM |
| GS8662R18E-333I | 72Mb SigmaCIO DDR-II Burst of 4 SRAM |
| GS8662R18GE-167 | 72Mb SigmaCIO DDR-II Burst of 4 SRAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| GS8662R18E-300 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb SigmaCIO DDR-II Burst of 4 SRAM |
| GS8662R18E-300I | 制造商:GSI Technology 功能描述:SRAM SYNC SGL 1.8V 72MBIT 4MX18 0.45NS 165FBGA - Trays |
| GS8662R18E-333 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb SigmaCIO DDR-II Burst of 4 SRAM |
| GS8662R18E-333I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb SigmaCIO DDR-II Burst of 4 SRAM |
| GS8662R18GE-167 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb SigmaCIO DDR-II Burst of 4 SRAM |
發布緊急采購，3分鐘左右您將得到回復。