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參數資料
| 型號： | GS8662S08E |
| 廠商： | GSI TECHNOLOGY |
| 英文描述： | 72Mb Burst of 2 DDR SigmaSIO-II SRAM |
| 中文描述： | 72Mb的DDR 2突發SigmaSIO - II SRAM的 |
| 文件頁數： | 1/37頁 |
| 文件大小： | 960K |
| 代理商： | GS8662S08E |
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Preliminary
GS8662S08/09/18/36E-333/300/250/200/167
72Mb Burst of 2
DDR SigmaSIO-II SRAM
333 MHz–167 MHz
1.8 V V
DD
1.8 V and 1.5 V I/O
165-Bump BGA
Commercial Temp
Industrial Temp
Rev: 1.01 9/2005
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
1/37
2005, GSI Technology
Features
Simultaneous Read and Write SigmaSIO Interface
JEDEC-standard pinout and package
Dual Double Data Rate interface
Byte Write controls sampled at data-in time
DLL circuitry for wide output data valid window and future
frequency scaling
Burst of 2 Read and Write
1.8 V +100/–100 mV core power supply
1.5 V or 1.8 V HSTL Interface
Pipelined read operation
Fully coherent read and write pipelines
ZQ mode pin for programmable output drive strength
IEEE 1149.1 JTAG-compliant Boundary Scan
Pin-compatible with future 144Mb devices
165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
RoHS-compliant 165-bump BGA package available
SigmaRAM
Family Overview
GS8662S08/09/18/36 are built in compliance with the
SigmaSIO-II SRAM pinout standard for Separate I/O
synchronous SRAMs. They are 75,497,472-bit (72Mb)
SRAMs. These are the first in a family of wide, very low
voltage HSTL I/O SRAMs designed to operate at the speeds
needed to implement economical high performance
networking systems.
165-Bump, 15 mm x 17 mm BGA
1 mm Bump Pitch, 11 x 15 Bump Array
JEDEC Std. MO-216, Variation CAB-1
Bottom View
Clocking and Addressing Schemes
A Burst of 2
SigmaSIO-II SRAM is a synchronous device. It
employs dual input register clock inputs, K and K. The device
also allows the user to manipulate the output register clock
input quasi independently with dual output register clock
inputs, C and C. If the C clocks are tied high, the K clocks are
routed internally to fire the output registers instead. Each Burst
of 2
SigmaSIO-II SRAM also supplies Echo Clock outputs,
CQ and CQ, which are synchronized with read data output.
When used in a source synchronous clocking scheme, the Echo
Clock outputs can be used to fire input registers at the data’s
destination.
Because Separate I/O Burst of 2 RAMs always transfer data in
two packets, A0 is internally set to 0 for the first read or write
transfer, and automatically incremented by 1 for the next
transfer. Because the LSB is tied off internally, the address
field of a Burst of 2 RAM is always one address pin less than
the advertised index depth (e.g., the 4M x 18 has a 1M
addressable index).
Parameter Synopsis
- 333
-300
-250
-200
-167
tKHKH
3.0 ns
3.3 ns
4.0 ns
5.0 ns
6.0 ns
tKHQV
0.45 ns
0.45 ns
0.45 ns
0.45 ns
0.5 ns
相關PDF資料 |
PDF描述 |
|---|---|
| GS8662S08E-167 | 72Mb Burst of 2 DDR SigmaSIO-II SRAM |
| GS8662S08E-167I | 72Mb Burst of 2 DDR SigmaSIO-II SRAM |
| GS8662S08E-200 | 72Mb Burst of 2 DDR SigmaSIO-II SRAM |
| GS8662S08E-200I | 72Mb Burst of 2 DDR SigmaSIO-II SRAM |
| GS8662S08E-250 | 72Mb Burst of 2 DDR SigmaSIO-II SRAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| GS8662S08E-167 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb Burst of 2 DDR SigmaSIO-II SRAM |
| GS8662S08E-167I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb Burst of 2 DDR SigmaSIO-II SRAM |
| GS8662S08E-200 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb Burst of 2 DDR SigmaSIO-II SRAM |
| GS8662S08E-200I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb Burst of 2 DDR SigmaSIO-II SRAM |
| GS8662S08E-250 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb Burst of 2 DDR SigmaSIO-II SRAM |
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