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參數資料
| 型號： | GS8662S08GE-200I |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | 72Mb Burst of 2 DDR SigmaSIO-II SRAM |
| 中文描述： | 8M X 8 DDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, MO-216CAB-1, FPBGA-165 |
| 文件頁數： | 12/37頁 |
| 文件大小： | 960K |
| 代理商： | GS8662S08GE-200I |
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Preliminary
GS8662S08/09/18/36E-333/300/250/200/167
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.01 9/2005
12/37
2005, GSI Technology
FLXDrive-II Output Driver Impedance Control
HSTL I/O SigmaSIO-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to V
SS
via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be 5X the
value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a
vendor-specified tolerance is between 150
and 300
. Periodic readjustment of the output driver impedance is necessary as the
impedance is affected by drifts in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts
in supply voltage and temperature every 1024 cycles. A clock cycle counter periodically triggers an impedance evaluation, resets
and counts again. Each impedance evaluation may move the output driver impedance level one step at a time towards the optimum
level. The output driver is implemented with discrete binary weighted impedance steps. Impedance updates for “0s” occur
whenever the SRAM is driving “1s” for the same DQs (and vice-versa for “1s”) or the SRAM is in HI-Z.
Separate I/O Burst of 2 Sigma SIO-II SRAM Truth Table
A
LD
R/W
Current
Operation
D
D
Q
Q
K
↑
(t
n
)
K
↑
(t
n
)
K
↑
(t
n
)
K
↑
(t
n
)
K
↑
(t
n+1
)
K
↑
(t
n+1
)
K
↑
(t
n+1
)
K
↑
(t
n+1
)
X
1
X
Deselect
X
—
Hi-Z
—
V
0
1
Read
X
—
Q0
Q1
V
0
0
Write
D0
D1
Hi-Z
—
Notes:
1.
2.
3.
4.
5.
“1” = input “high”; “0” = input “low”; “V” = input “valid”; “X” = input “don’t care”
“—” indicates that the input requirement or output state is determined by the next operation.
Q0 and Q1 indicate the first and second pieces of output data transferred during Read operations.
D0 and D1 indicate the first and second pieces of input data transferred during Write operations.
Qs are tristated for one cycle in response to Deselect and Write commands, one cycle after the command is sampled, except when pre-
ceded by a Read command.
CQ is never tristated.
Users should not clock in metastable addresses.
6.
7.
相關PDF資料 |
PDF描述 |
|---|---|
| GS8662S08GE-250 | 72Mb Burst of 2 DDR SigmaSIO-II SRAM |
| GS8662S08GE-250I | 72Mb Burst of 2 DDR SigmaSIO-II SRAM |
| GS8662S08GE-300 | 72Mb Burst of 2 DDR SigmaSIO-II SRAM |
| GS8662S08GE-300I | 72Mb Burst of 2 DDR SigmaSIO-II SRAM |
| GS8662S08GE-333 | 72Mb Burst of 2 DDR SigmaSIO-II SRAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| GS8662S08GE-250 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb Burst of 2 DDR SigmaSIO-II SRAM |
| GS8662S08GE-250I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb Burst of 2 DDR SigmaSIO-II SRAM |
| GS8662S08GE-300 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb Burst of 2 DDR SigmaSIO-II SRAM |
| GS8662S08GE-300I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb Burst of 2 DDR SigmaSIO-II SRAM |
| GS8662S08GE-333 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb Burst of 2 DDR SigmaSIO-II SRAM |
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