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參數(shù)資料

Instruction Register

ID Code Register

31 30 29

Boundary Scan Register

· · ·

Bypass Register

TDI

TDO

TMS

TCK

Test Access Port (TAP) Controller

Control Signals

GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D)

Rev: 1.05 11/2005

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

26/39

2002, GSI Technology

JTAG TAP Block Diagram

Identification (ID) Register

The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in

Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.

It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the

controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.

相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
GS88136BGT-200I	制造商:GSI 制造商全稱:GSI Technology 功能描述:512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
GS88136BGT-200IV	制造商:GSI 制造商全稱:GSI Technology 功能描述:512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
GS88136BGT-200V	制造商:GSI 制造商全稱:GSI Technology 功能描述:512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
GS88136BGT-250	制造商:GSI 制造商全稱:GSI Technology 功能描述:512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
GS88136BGT-250I	制造商:GSI 制造商全稱:GSI Technology 功能描述:512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs

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