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參數(shù)資料
| 型號： | GS88136BT-333I |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | 512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs |
| 中文描述： | 256K X 36 CACHE SRAM, 4.5 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 1/39頁 |
| 文件大小： | 791K |
| 代理商： | GS88136BT-333I |
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GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D)
512K x 18, 256K x 32, 256K x 36
9Mb Sync Burst SRAMs
333 MHz
–
150 MHz
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
100-pin TQFP & 165-bump BGA
Commercial Temp
Industrial Temp
Rev: 1.05 11/2005
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
1/39
2002, GSI Technology
Features
IEEE 1149.1 JTAG-compatible Boundary Scan
2.5 V or 3.3 V +10%/–10% core power supply
2.5 V or 3.3 V I/O supply
LBO pin for Linear or Interleaved Burst mode
Internal input resistors on mode pins allow floating mode pins
Byte Write (BW) and/or Global Write (GW) operation
Internal self-timed write cycle
Automatic power-down for portable applications
JEDEC-standard 100-lead TQFP and 165-bump BGA
packages
RoHS-compliant 100-lead TQFP and 165-bump BGA
packages available
Functional Description
Applications
The GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D) is a
9,437,184-bit high performance synchronous SRAM with a 2-
bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main
store to networking chip set support.
Controls
Addresses, data I/Os, chip enable (E1, E2), address burst
control inputs (ADSP, ADSC, ADV) and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
SCD Pipelined Reads
The GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D) is a
SCD (Single Cycle Deselect) pipelined synchronous SRAM.
DCD (Dual Cycle Deselect) versions are also available. SCD
SRAMs pipeline deselect commands one stage less than read
commands. SCD RAMs begin turning off their outputs
immediately after the deselect command has been captured in
the input registers.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D)
operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V
and 2.5 V compatible. Separate output power (V
DDQ
) pins are
used to decouple output noise from the internal circuits and are
3.3 V and 2.5 V compatible.
Paramter Synopsis
-333
2.5
3.0
-300
2.5
3.3
-250
2.5
4.0
-200
3.0
5.0
-150
3.8
6.7
Unit
ns
ns
Pipeline
3-1-1-1
t
KQ
tCycle
Curr (x18)
Curr (x32/x36)
t
KQ
tCycle
Curr (x18)
Curr (x32/x36)
250
290
4.5
4.5
200
230
230
265
5.0
5.0
185
210
200
230
5.5
5.5
160
185
170
195
6.5
6.5
140
160
140
160
7.5
7.5
128
145
mA
mA
ns
ns
mA
mA
Flow Through
2-1-1-1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS88136BT-150V | 512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs |
| GS88132BT-150IV | 512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs |
| GS88132BT-150V | 512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs |
| GS88132BT-200IV | 512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs |
| GS88132BT-200V | 512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS88136CD-200 | 制造商:GSI Technology 功能描述:SRAM SYNC SGL 2.5V/3.3V 9MBIT 256KX36 6.5NS/3NS 165FPBGA - Trays |
| GS88136CD-200I | 制造商:GSI Technology 功能描述:SRAM SYNC SGL 2.5V/3.3V 9MBIT 256KX36 6.5NS/3NS 165FPBGA - Trays |
| GS88136CD-250 | 制造商:GSI Technology 功能描述:SRAM SYNC SGL 2.5V/3.3V 9MBIT 256KX36 5.5NS/2.5NS 165FPBGA - Trays |
| GS88136CD-300 | 制造商:GSI Technology 功能描述:SRAM SYNC SGL 2.5V/3.3V 9MBIT 256KX36 5NS/2.5NS 165FPBGA - Trays |
| GS88136CD-333 | 制造商:GSI Technology 功能描述:SRAM SYNC SGL 2.5V/3.3V 9MBIT 256KX36 4.5NS/2.5NS 165FPBGA - Trays |
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