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參數資料
| 型號： | GT-48002A |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | Switched Fast Ethernet Controller for 100BaseX(100BaseX交換式快速以太網控制器) |
| 中文描述： | 交換式快速以太網控制器（100BaseX交換式快速以太網控制器的100BaseX） |
| 文件頁數： | 1/102頁 |
| 文件大小： | 1001K |
| 代理商： | GT-48002A |
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GT-48002A
Switched Fast Ethernet Controller
for 100BaseX
Preliminary Rev.
Revision 1.2
8/19/97
Please contact Galileo Technology for possible
updates before finalizing a design.
FEATURES
www.galileoT.com
support@galileoT.com
Tel: +1-408.451.1400
Fax: +1-408.451.1404
Single-chip, low cost, Switched Fast Ethernet
Controller
- Provides packet switching functions between two
10/100Mbps, auto-negotiated on-chip Fast
Ethernet ports and the PCI expansion port
- Switch expansion via 1Gbps PCI bus
- Ideal uplink/server connect for the 10 Mbps GT-
48001A Switched Ethernet Controller
GalNet Architecture Family Member
- Connects seamlessly to other GalNet Family
Devices including GT-48001A 10BaseX and GT-
48003 100VG-AnyLAN controllers
Incorporates two 802.3 compliant 10/100Mbps Media
Access Controllers
- Direct Interface to MII (Media Independent
Interface)
- Half/Full Duplex Support (up to 200 Mbps/port)
- IEEE 802.3 100Base-TX, T4, and FX compatible
Full MII Management Support (MDC/MDIO) via CPU
Auto-negotiation supported through MII Interface
CRC generation for CPU generated packets
High-Performance Distributed Switching Engine
- Performs forwarding and filtering at full wire speed
- 148,800 packets/s on each Ethernet port
- Flexible software or hardware intervention in
packet routing decisions
Direct support for packet buffering
- Glueless interface to 1or 2Mbyte of 60ns EDO
DRAM
- Up to 1K buffers, 1536-bytes each, dynamically
allocated to the receive and PCI ports
Supports ‘Store and Forward’ switching approach
- Low last-bit in to first-bit out delay
- Allows bridging between higher/lower speed
interfaces (FDDI, ATM, WAN)
High observability LED interface
- 6 parallel LED outputs per port, including internal
“monostable” function to enable viewing of
dynamic signals
- 3 pin serial LED interface for additional status
information per port
Advanced address recognition
- Intelligent address recognition mechanism enables
forwarding rate at full wire speed
- Self-learning mechanism
- Supports up to 8K Unicast addresses and
unlimited Multicast/Broadcast addresses
- Broadcast storm filtering
PCI Rev 2.1 interface for switch expansion and
management CPU connection
- Up to 3 GT-48002A devices per PCI bus segment
without PCI-to-PCI bridging
- Up to 32 GalNet devices in a single switch
- Standard CPU connection for management
- Simple interface to other networking interfaces
(ATM, FDDI, etc.)
Extensive network management support
- Repeater MIB and PCI counters
- Address aging support
- Hardware assist for Spanning Tree algorithm
- RMON Station-to-Station connectivity matrix
- CPU access to Address Table
- Ability to define static addresses
- Monitoring (sniffer) mode
HP-EASE Packet sampling management technology
- Takes “snapshots” of packets at programmable
intervals
- Allows for the implementation of HP-EASE or
sampled RMON with low-cost CPUs
208 pin PQFP package
DMA
Transmit
Receive
Collision
Forwarding Unknown
Sniffer
Half/Full Duplex
Status
Switching
Engine
PCI Bus
Data
Address
Control
Self-Learning &
Address
Recognition
Engine
DRAM
Controller
Frame
Controller
GALNET
Controller
RMON FIFO
Control
PCI Counters
2 x MIB Counters
PCI
Address Table
Statistics Counters
Configuration Registers
Intervention
Mode
Control
Packet Buffers
Serial
Switching
GALNET
Sniffer
Control
Miscellaneous
2x
LED
Control
DMA
PCI Bus Controller
10/100 Mbps
MII
Interface
Port 0
Rx
FIFO
Tx
FIFO
10/100 Mbps
MII
Interface
Port 1
Rx
FIFO
Tx
FIFO
Receive Buffer Full
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