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參數資料
| 型號： | GT-64010A |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | System Controller with PCI Interface for R4XXX/ R5000 Family CPUs(帶PCI接口用于R4XXX/ R5000 系列 CPUs的系統控制器) |
| 中文描述： | 系統控制器的PCI R4XXX接口/ R5000系列處理器（帶的PCI接口用于R4XXX / R5000系列處理器的系統控制器） |
| 文件頁數： | 1/111頁 |
| 文件大小： | 671K |
| 代理商： | GT-64010A |
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W e b : w w w . g al il eoT.com
E m ai l: i n fo @ g al i leoT. co m Tel : ( 408) 451- 1400 Fax: ( 4 08 ) 451- 1404
System Controller with
PCI Interface for R4XXX/
R5000 Family CPUs
GT-64010A
Preliminary
Revision 1.1
December 1996
FEATURES
NOTE: Always contact Galileo Technology for
possible updates before starting a design.
Galileo
TechnologyTM
Integrated system controller with PCI bus interface for
high performance embedded controller applications
Supports the R4600/4650/4700/R5000 CPUs
Up to 50MHz CPU bus frequency
64 byte write buffer
- 64-bit wide
- 8 levels deep
256KB or 512KB zero-wait-state secondary cache
support by using GT-64012 (R4600/R4700)
DRAM controller
- Page mode and EDO DRAMs
- 512MB address space
- 256KB-16MB device depth
- 1- 4 banks supported directly
- 32-bit or 64-bit data width
- Different size for each bank
Device controller
- 5 chip selects
- Programmable timing for each chip select
- Supports several types of standard memories
(ROM / Flash / SRAM) and I/O controllers
- Up to 160MB address space
- External wait support
- 8-,16-,32- and 64-bit width device (and boot) sup-
port
External parity support for user selected banks of
DRAM and devices
DMA controller
- Four independent channels
- Chaining via linked lists of records
- Byte alignment on source and destination
- Transfers through a 32-byte internal FIFO
- Moves data between PCI, memory, and devices
PCI bus
- Fully compatible with PCI 2.1 Specification
- High performance PCI interfaces via 96-bytes of
posted write and read prefetch buffers
- 32-bit PCI master and slave operations
- Provides clock speed of up to 33MHz with no wait
states on PCI (asynchronous from CPU bus)
- Supports burst operations on PCI for efficient data
transfer
- Supports doorbells between Host and PCI
- Supports flexible byte swapping - no need for CPU
intervention.
- Synchronization Barrier support from CPU to PCI
and from PCI to CPU.
Host to PCI bridge
- Translates CPU cycles into PCI I/O or Memory
cycles
- Generates configuration Interrupt Acknowledge
and Special cycles on PCI
PCI to Main Memory bridge
- Supports fast back-to-back transactions
- Flexible address mapping of both DRAM and
devices from PCI side
- Supports memory and I/O transactions to internal
configuration registers
- Supports locked operations
PCI configuration registers are accessed from both
CPU and PCI side
Three 24-bit wide and one 32-bit wide timers/counters
5V Operation (3.3V operation using inexpensive sup-
port components
256 PQFP or 272 Ball-BGA
R4xxx CPU
DRAM
Flash
GT-64010A
SCSI
Network
PCI Bus
Other
SysAD Bus
Address
&
Control
Data
BYPASS
32
64
I/O
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| GT5-2/1S-HU | RECTANGULAR CONNECTOR |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| GT64010A-B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
| GT64010AB1 | 制造商:GALILEO 功能描述:* |
| GT64010A-P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
| GT64011-A1-PBB-C000 | 制造商:Marvell 功能描述: |
| GT64115-A2-PBB-C000 | 制造商:Marvell 功能描述: 制造商:Marvell 功能描述:Marvell GT64115-A2-PBB-C000 |
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