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參數(shù)資料
| 型號(hào)： | HA9P4905-5Z |
| 廠(chǎng)商： | INTERSIL CORP |
| 元件分類(lèi)： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | Precision Quad Comparators |
| 中文描述： | QUAD COMPARATOR, 10000 uV OFFSET-MAX, 180 ns RESPONSE TIME, PDSO16 |
| 封裝： | LEAD FREE, SOIC-16 |
| 文件頁(yè)數(shù)： | 4/8頁(yè) |
| 文件大小： | 241K |
| 代理商： | HA9P4905-5Z |
4
Applying the HA-4900 Series Comparators
Supply Connections
This device is exceptionally versatile in working with most
available power supplies. The voltage applied to the V+ and V-
terminals determines the allowable input signal range; while the
voltage applied to the V
L
+ and V
L
- determines the output
swing. In systems where dual analog supplies are available,
these would be connected to V+ and V-, while the logic supply
and return would be connected to V
LOGIC
+ and V
LOGIC
-. The
analog and logic supply commons can be connected together
at one point in the system, since the comparator is immune to
noise on the logic supply ground. A negative output swing may
be obtained by connecting V
L
+ to ground and V
L
- to a negative
supply. Bipolar output swings (15V
P-P
, Max) may be obtained
using dual supplies. In systems where only a single logic supply
is available (+5V to 15V), V+ and V
LOGIC
+ may be connected
together to the positive supply while V- and V
LOGIC
- are
grounded. If an input signal could swing negative with respect
the V- terminal, a resistor should be connected in series with
the input to limit input current to < 5mA since the C-B junction of
the input transistor would be forward biased.
Unused Inputs
Inputs of unused comparator sections should be tied to a
differential voltage source to prevent output “chatter.”
Crosstalk
Simultaneous high frequency operation of all other channels
in the package will not affect the output logic state of a given
channel, provided that its differential input voltage is
sufficient to define a given logic state (
V
IN
≥
±
V
OS
). Low
level or high impedance input lines should be shielded from
other signal sources to reduce crosstalk and interference.
Power Supply Decoupling
Decouple all power supply lines with 0.01
μ
F ceramic capacitors
to ground line located near the package to reduce coupling
between channels or from external sources.
Response Time
Fast rise time (<200ns) input pulses of several volts
amplitude may result in delay times somewhat longer than
those illustrated for 100mV steps. Operating speed is
optimized by limiting the maximum differential input voltage
applied, with resistor-diode clamping networks.
Typical Applications
Data Acquisition System
In this circuit the HA-4900 series is used in conjunction with
a D to A converter to form a simple, versatile, multi-channel
analog input for a data acquisition system. In operation the
processor first sends an address to the D to A, then the
processor reads the digital word generated by the
comparator outputs. To perform a simple comparison, the
processor sets the D to A to a given reference level, then
examines one or more comparator outputs to determine if
their inputs are above or below the reference. A window
comparison consists of two such cycles with 2 reference
levels set by the D to A. One way to digitize the inputs would
be for the processor to increment the D to A in steps. The D
to A address, as each comparator switches, is the digitized
level of the input. While stairstepping the D to A is slower
than successive approximation, all channels are digitized
during one staircase ramp.
Schematic Diagram
Q
9D
BIAS 2
ONE FOURTH ONLY
R
20D
1k
R
20C
1k
R
20B
1k
R
20A
1k
Q
9C
Q
9B
Q
9A
R
21
1k
Q
10
D
9A
BIAS 1
Q
5
R
16
540
Q
4
D
4A
D
4B
Q
4C
Q
3
PR
1
200k
R
10
4k
Q
2
Q
1
R
9
4k
BIAS 3
BIAS 4
Q
11
+IN
Q
17
Q
18
Q
12
Q
13
R
1
500
R
2
13k
R
3
1k
Q
19
Q
20
Q
14
R
4
1k
Q
21
Q
22
-IN
M
N1
R
2.5k
R
6
2.5k
Q
16
Q
7
Q
23
R
5
360
M
N2
M
N3
Q
24
Q
25
R
18
664
Q
38
M
N4
D
45
D
11A
Q
26
R
17
19k
R
14
5k
Q
33
Q
34
Q
36
Q
37
Q
30
Q
28
R
11
8k
R
15
8k
Q
31
R
23
100
R
24
14k
D
29B
Q
29
Q
29A
R
22
100
R
12
8k
Q
32
M
N6
M
N5
V
LOGIC
-
OUT
V
LOGIC
+
V-
V+
Q
15
D
35
D
39
HA-4900, HA-4902, HA-4905
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