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參數(shù)資料
| 型號： | HC163 |
| 廠商： | System Logic Semiconductor Co., Ltd. |
| 元件分類： | 通用總線功能 |
| 英文描述： | Presettable Counters |
| 中文描述： | 可預(yù)置計數(shù)器 |
| 文件頁數(shù)： | 5/9頁 |
| 文件大小： | 86K |
| 代理商： | HC163 |
SL74HC163
S ystem Logic
Semiconductor
SLS
TIMING REQUIREMENTS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Guaranteed Limit
Symbol
Parameter
V
25
°
C to
-55
°
C
≤
85
°
C
≤
125
°
C
Unit
t
su
Minimum Setup Time, Preset Data Inputs to Clock
(Figure 4)
2.0
4.5
6.0
40
15
12
60
20
18
80
30
20
ns
t
su
Minimum Setup Time, Load to Clock
(Figure 4)
2.0
4.5
6.0
60
15
12
75
20
18
90
30
20
ns
t
su
Minimum Setup Time, Reset to Clock
(Figure 3)
2.0
4.5
6.0
60
20
17
75
25
23
90
35
25
ns
t
su
Minimum Setup Time, Enable T or Enable P to
Clock (Figure 5)
2.0
4.5
6.0
80
20
17
95
25
23
110
35
25
ns
t
h
Minimum Hold Time, Clock to Load or Preset Data
Inputs (Figure 4)
2.0
4.5
6.0
3
3
3
3
3
3
3
3
3
ns
t
h
Minimum Hold Time, Clock to Reset
(Figure 3)
2.0
4.5
6.0
3
3
3
3
3
3
3
3
3
ns
t
h
Minimum Hold Time, Clock to Enable T or Enable
P (Figure 5)
2.0
4.5
6.0
3
3
3
3
3
3
3
3
3
ns
t
rec
Minimum Recovery Time, Load Inactive to Clock
(Figure 4)
2.0
4.5
6.0
80
15
12
95
20
17
110
26
23
ns
t
w
Minimum Pulse Width, Clock (Figure 1)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
t
w
Minimum Pulse Width, Reset (Figure 3)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
t
r,
t
f
Maximum Input Rise and Fall Times
(Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns
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