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參數資料
| 型號： | HC595 |
| 廠商： | System Logic Semiconductor Co., Ltd. |
| 英文描述： | 8-Bit Serial-Input/Serial or Parallel-Output Shift Register with Latched 3-State Outputs |
| 中文描述： | 8位Serial-Input/Serial或并行輸出移位與鎖存3注冊態輸出 |
| 文件頁數： | 5/10頁 |
| 文件大小： | 81K |
| 代理商： | HC595 |
SL74HC595
S ystem Logic
Semiconductor
SLS
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Guaranteed Limit
Symbol
Parameter
V
25
°
C to
-55
°
C
≤
85
°
C
≤
125
°
C
Unit
f
max
Minimum Clock Frequency (50% Duty Cycle)
(Figures 1and 7)
2.0
4.5
6.0
6.0
30
35
4.8
24
28
4.0
20
24
MHz
t
PLH
, t
PHL
Maximum Propagation Delay, Shift Clock to SQ
H
(Figures 1and 7)
2.0
4.5
6.0
140
28
24
175
35
30
210
42
36
ns
t
PHL
Maximum Propagation Delay , Reset to SQ
H
(Figures 2 and 7)
2.0
4.5
6.0
145
29
25
180
36
31
220
44
38
ns
t
PLH
, t
PHL
Maximum Propagation Delay , Latch Clock to Q
A
-
Q
H
(Figures 3 and 7)
2.0
4.5
6.0
140
28
24
175
35
30
210
42
36
ns
t
PLZ
, t
PHZ
Maximum Propagation Delay , Output Enable to
Q
A
-Q
H
(Figures 4 and 8)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
t
PZL
, t
PZH
Maximum Propagation Delay , Output Enable to
Q
A
-Q
H
(Figures 4 and 8)
2.0
4.5
6.0
135
27
23
170
34
29
205
41
35
ns
t
TLH
, t
THL
Maximum Output Transition Time, Q
A
-Q
H
(Figures
3 and 7)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
t
TLH
, t
THL
Maximum Output Transition Time, SQ
H
(Figures 1 and 7)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
C
IN
Maximum Input Capacitance
-
10
10
10
pF
C
OUT
Maximum Three-State Output Capacitance
(Output in High-Impedance State), Q
A
-Q
H
-
15
15
15
pF
Power Dissipation Capacitance (Per Package)
Typical @25
°
C,V
CC
=5.0 V
C
PD
Used to determine the no-load dynamic power
consumption:
P
D
=C
PD
V
CC
2
f+I
CC
V
CC
300
pF
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