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參數資料
| 型號： | HC652 |
| 廠商： | System Logic Semiconductor Co., Ltd. |
| 英文描述： | EPROM IC; Memory Size:128Kbit; Memory Configuration:16K x 8; Access Time, Tacc:250ns; Package/Case:28-DIP; EPROM Type:Parallel UV Erasable; Supply Voltage Nom, Vcc:5V; Mounting Type:Through Hole; Voltage Rating:5V |
| 中文描述： | 八路三態總線收發器和D觸發器 |
| 文件頁數： | 6/9頁 |
| 文件大小： | 79K |
| 代理商： | HC652 |
SL74HC652
S ystem Logic
Semiconductor
SLS
FUNCTION TABLE
A
INPUTS
Z
Dir.
L
OE
H
CAB CBA SAB SBA
X
X
B
FUNCTION
INPUTS
Z
Both the A bus and the B bus are inputs.
The output functions of the A and B bus
are disabled.
Both the A and B bus are used for inputs
to the internal flip-flops. Data at the bus
will be stored on low to high transition of
the clock inputs.
The A bus are outputs and the B bus are
inputs.
The data at the B bus are displayed at the
A bus.
The data at the B bus are displayed at the
A bus. The data of the B bus are stored to
the internal flip-flops on low to high
transition of the clock pulse.
The data stored to the internal flip-flops,
are displayed at the A bus.
The data at the B bus are stored to the
internal flip-flops on low to high transition
of the clock pulse. The states of the
internal flip-flops output directly to the A
bus.
OUTPUTS The A bus are inputs and the B bus are
outputs.
L
H
B bus.
L
H
A bus. The data of the B bus are stored to
the internal flip-flops on low to high
transition of the clock pulse.
Qn
The data stored to the internal flip-flops
are displayed at the B bus.
L
H
internal flip-flops on low to high transition
of the clock pulse. The states of the
internal flip-flops output directly to the B
bus.
OUTPUTS Both the A bus and the B bus are outputs
Qn
The data stored to the internal flip-flops
are displayed at the A and B bus
respectively.
Qn
The output at the A bus are displayed at
the B bus, the output at the B bus are
displayed at the A bus respec.
X
X
X
X
INPUTS
INPUTS
OUTPUTS
INPUTS
X
*
X
X
L
L
H
L
H
L
H
L
H
L
L
X
*
X
L
X
*
X
X
H
Qn
X
X
*
X
H
H
L
H
L
INPUTS
X
X
*
L
X
L
H
L
H
The data at the A bus are displayed at the
H
H
X
*
L
X
The data at the B bus are displayed at the
X
X
*
H
X
X
X
*
H
X
L
H
The data at the A bus are stored to the
OUTPUTS
Qn
H
L
X
X
H
H
H
H
Qn
X : DON’T CARE
Z : HIGH IMPEDANCE
Qn : THE DATA STORED TO THE INTERNAL FLIP-FLOPS BY MOST RECENT LOW TO HIGH TRANSITION
OF THE CLOCK INPUTS
*
: THE DATA AT THE A AND B BUS WILL BE STORED TO THE INTERNAL FLIP-FLOPS ON EVERY LOW TO
TRANSITION OF THE CLOCK INPUTS
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